Chapter 2. Programming Model
2-5
The MPC7400 Processor Register Set
òXER Register (XER),ó in Chapter 2, òPowerPC Register Set,ó of
The
Programming Environments Manual
for more information.
Implementation Note
To allow emulation of the
lscbx
instruction deTned by
the POWER architecture, XER[16D23] are implemented so that they can be read
with
mfspr
[XER] and written with
mtspr
[XER] instructions.
Link register (LR). The LR provides the branch target address for the Branch
Conditional to Link Register (
bclr
x
) instruction, and can be used to hold the
logical address of the instruction that follows a branch and link instruction,
typically used for linking to subroutines. See òLink Register (LR),ó in Chapter 2,
òPowerPC Register Set,ó of
The Programming Environments Manual
.
Count register (CTR). The CTR holds a loop count that can be decremented
during execution of appropriately coded branch instructions. The CTR can also
provide the branch target address for the Branch Conditional to Count Register
(
bcctr
x
) instruction. See òCount Register (CTR),ó in Chapter 2, òPowerPC
Register Set,ó of
The Programming Environments Manual
.
Vector save/restore register (VRSAVE). The VRSAVE register is deTned by the
AltiVec technology to assist application and operating system software in saving
and restoring the architectural state across process context-switched events. See
Section 7.1.1.5, òVector Save/Restore Register (VRSAVE).ó
User-level registers
(VEA)The PowerPC VEA deTnes the time base facility
(TB), which consists of two 32-bit registerstime base upper (TBU) and time base
lower (TBL). The time base registers can be written only by supervisor-level
instructions but can be read by both user- and supervisor-level software. For more
information, see òPowerPC VEA Register SetTime Base,ó in Chapter 2,
òPowerPC Register Set,ó of
The Programming Environments Manual
.
Supervisor-level registers
(OEA)The OEA deTnes the registers an operating
system uses for memory management, conTguration, exception handling, and other
operating system functions. The OEA deTnes the following supervisor-level
registers for 32-bit implementations:
ConTguration registers
D Machine state register (MSR). The MSR deTnes the state of the processor.
The MSR can be modiTed by the Move to Machine State Register
(
mtmsr
),
System Call (
sc
), and Return from Exception (
rT
) instructions. It can be read
by the Move from Machine State Register (
mfmsr
) instruction. When an
exception is taken, the contents of the MSR are saved to the machine status
save/restore register 1 (SRR1), which is described below. See òMachine State
Register (MSR),ó in Chapter 2, òPowerPC Register Set,ó of
The Programming
Environments Manual
for more information.
Implementation Note
Table 2-1 describes MSR bits the MPC7400
implements that are not required by the PowerPC architecture.
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