Chapter 4. Exceptions
4-25
Exception DeTnitions
4.6.14 Instruction Address Breakpoint Exception (0x01300)
An instruction address breakpoint interrupt occurs when the following conditions are met:
¥
The instruction breakpoint address IABR[0D29] matches EA[0D29] of the next
instruction to complete in program order. The instruction that triggers the instruction
address breakpoint exception is not executed before the exception handler is
invoked.
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The translation enable bit (IABR[TE]) matches MSR[IR].
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The breakpoint enable bit (IABR[BE]) is set. The address match is also reported to
the JTAG/COP block, which may subsequently generate a soft or hard reset. The
instruction tagged with the match does not complete before the breakpoint exception
is taken.
Table 4-11 lists register settings when an instruction address breakpoint exception is taken.
The MPC7400 requires that an
mtspr
to the IABR be followed by a context-synchronizing
instruction. The MPC7400 cannot generate a breakpoint response for that
context-synchronizing instruction if the breakpoint is enabled by the
mtspr
[IABR]
immediately preceding it. The MPC7400 also cannot block a breakpoint response on the
context-synchronizing instruction if the breakpoint was disabled by the
mtspr
[IABR]
instruction immediately preceding it. The format of the IABR register is shown in
Section 2.1.2.1, òInstruction Address Breakpoint Register (IABR).ó
When an instruction address breakpoint exception is taken, instruction fetching resumes as
offset 0x01300 from the base address indicated by MSR[IP].
4.6.15 System Management Interrupt (0x01400)
The MPC7400 implements a system management interrupt exception, which is not deTned
by the PowerPC architecture. The system management exception is very similar to the
external interrupt exception and is particularly useful in implementing the nap mode. It has
Table 4-11. Instruction Address Breakpoint ExceptionRegister Settings
Register
Setting Description
SRR0
Set to the effective address of the instruction that the processor would have attempted to execute next
if no exception conditions were present.
SRR1
0D5
6
7D15 Cleared
16D31Loaded with equivalent MSR bits
Cleared
Loaded with equivalent MSR bit
MSR
VEC 0
POW 0
ILE
EE
LE
0
Set to value of ILE
PR
FP
ME
FE0
0
0
0
SE
BE
FE1
IP
0
0
0
IR
DR
PM
RI
0
0
0
0