Chapter 8. Signal Descriptions
8-1
Chapter 8
Signal Descriptions
This chapter describes the MPC7400 microprocessors external signals. It contains a
concise description of individual signals, showing behavior when the signal is asserted,
negated, or tristated, and when the signal is an input or an output.
NOTE:
A bar over a signal name indicates that the signal is active
lowfor example, ARTRY (address retry) and TS (transfer
start). Active-low signals are referred to as asserted (active)
when they are low and negated when they are high. Signals that
are not active low, such as AP[0:3] (address bus parity signals)
and TT[0:4] (transfer type signals) are referred to as asserted
when they are high and negated when they are low.
The MPC7400 provides a mode switch (via the EMODE signal) that enables either the 60x
bus protocol or MPX bus protocol operation. The 60x bus interface implements the protocol
described in the
PowerPC Microprocessor Family: The Bus Interface for 32-Bit
Microprocessors
; note that although this protocol is implemented by the MPC603e,
MPC604 and MPC740/750 processors, it is referenced as the 60x bus interface. The MPX
bus mode includes several additional features that allow it to provide higher memory
bandwidth than the 60x bus.
Refer to the MPC7400 hardware speciTcation for detailed electrical and mechanical
information for each signal.
8.1 Signal Groupings
The MPC7400 60x bus and MPX bus interface protocol signals are grouped as follows:
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Address arbitrationThe MPC7400 uses these signals to arbitrate for address bus
mastership.
Address transfer startThese signals indicate that a bus master has begun a
transaction on the address bus.
Address transferThese signals include the address bus and address parity signals.
They are used to transfer the address and to ensure the integrity of the transfer.
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