
Chapter 7. The AltiVec Technology Implementation
7-15
AltiVec Technology and the Cache Model
The MPC7400 detects underows and production of denormalized numbers on vector oat
results before rounding, not after. Future versions of the
AltiVec Technology Programming
Environments Manual
may reect this ordering.
7.2 AltiVec Technology and the Cache Model
The MPC7400 uses a uniTed LSU to load and store operands into the GPRs, FPRs, and
VRs. The MPC7400s high-bandwidth memory subsystem supports anticipated AltiVec
workloads.
The memory subsystem features summarized in the following sections combine to provide
high bandwidth while maintaining latencies and cache capacities similar to the MPC750.
The following list summarizes features of the MPC7400 L1 cache implementation that are
affected by the AltiVec implementation:
¥
The 32-Kbyte 8-way set associative data cache is fully non-blocking.
128-bit interface designed to support AltiVec load/store operations.
Supports both MRU (most-recently-used) and LRU (least-recently-used) vector
loads.
New castout and modiTed bits support
lvx
/
stvx
LRU operations.
Pseudo LRU (PLRU) replacement algorithm
¥
¥
Support for AltiVec LRU instructions. LRU instructions are described in
Section 7.1.2.1, òLRU Instructions.ó
¥
Support for AltiVec transient instructions. Transient instructions are described in
Section 7.1.2.2, òTransient Instructions.ó
7.3 AltiVec and the Exception Model
Only the three following exceptions can result from execution of an AltiVec instruction:
¥
An AltiVec unavailable exception occurs with an attempt to execute any non-stream
AltiVec instruction with MSR[VEC] = 0. After this exception occurs, execution
resumes at offset 0x00F20 from the base real address indicated by MSR[IP]. This
exception does not happen for data streaming instructions (
dst(t)
,
dstst(t)
, and
dss
).
Also note that VRSAVE is not protected by this exception which is consistent with
the AltiVec PEM. In other words, any access to the VRSAVE register will not cause
an exception when MSR[VEC] = 0.