INDEX
Index-10
MPC7400 RISC Microprocessor Users Manual
AltiVec register file,
7-2
AltiVec-specific registers,
1-28
implementation-specific
BAMR,
2-20
,
11-9
HID1,
2-15
IABR,
2-10
ICTC,
2-23
L2CR,
2-28
,
3-55
list of implementation-specific registers,
1-29
MMCR
n
,
2-16
D
2-20
,
4-24
,
11-4
D
11-9
,
11-12
MSSCR0,
2-26
,
9-7
PMC
n
,
2-21
,
4-24
,
11-10
,
11-13
D
11-21
SIAR,
2-22
,
4-24
,
11-11
THRM
n
,
2-23
,
10-8
UBAMR,
2-21
,
11-9
UMMCR
n
,
2-18
D
2-20
,
11-7
D
11-9
UPMC
n
,
2-22
,
11-11
USIAR,
2-22
,
11-11
not implemented
SDA,
2-22
USDA,
2-22
performance monitor registers,
2-15
,
11-4
programming model,
2-3
register set,
2-3
reset settings,
2-32
SPR encodings,
2-61
supervisor-level
BAMR,
2-20
,
11-9
BAT registers,
2-6
DABR,
2-8
DAR,
2-7
DEC,
2-8
DSISR,
2-7
EAR,
2-8
HID0,
2-11
,
10-3
HID1,
2-15
IABR,
2-10
ICTC,
2-23
L2CR,
2-28
,
3-55
list of supervisor-level registers,
1-29
MMCR
n
,
2-16
D
2-20
,
4-24
,
11-4
D
11-9
,
11-12
MSR,
2-5
MSSCR0,
2-26
,
9-7
performance monitor SPRs,
11-4
PMC
n
,
2-21
,
4-24
,
11-10
,
11-13
D
11-21
PVR,
2-6
SDR1,
2-7
SIAR,
2-22
,
4-24
,
11-11
SPRG
n
,
2-7
SPRs for performance monitor,
11-3
SR
n
,
2-7
SRR0/SRR1,
2-7
THRM
n
,
2-23
,
10-8
time base (TB),
2-8
user-level
CR,
2-4
CTR,
2-5
FPR
n
,
2-4
FPSCR,
2-4
GPR
n
,
2-4
LR,
2-5
performance monitor SPRs,
11-4
time base (TB),
2-5
,
2-8
UBAMR,
2-21
,
11-9
UMMCR
n
,
2-18
D
2-20
,
11-7
D
11-9
UPMC
n
,
2-22
,
11-11
USIAR,
2-22
,
11-11
VR
n
,
2-4
VRSAVE,
2-5
,
7-4
VSCR,
2-4
,
7-2
XER,
2-4
VR
n
,
7-2
Rename buffer, definition,
6-3
Rename register operation,
6-21
Reservation station, definition,
6-3
Reserved instruction class,
2-38
Reset
HRESET signal,
8-44
,
9-58
reset exception,
4-15
settings at power-on,
2-32
SRESET signal,
8-44
,
9-58
Retirement, definition,
6-3
rfi,
4-13
Rotate/shift instructions,
2-45
,
2-76
,
A-27
Rounding/conversion instructions, vector FP,
2-78
RSRV (reservation) signal,
8-46
,
9-59
S
SDA (sampled data address) register,
2-22
SDR1 register,
2-7
Segmented memory model,
see
Memory
management unit
Serializing instructions,
6-21
SHD
n
(shared) signal,
8-17
,
8-33
,
9-24
,
9-47
Shift/rotate instructions,
2-45
,
A-27
SIAR (sampled instruction address
register),
2-22
,
4-24
,
11-11
Signals
60x bus mode
AACK,
8-15
ABB,
8-9
,
9-10
address arbitration signals,
8-8
,
9-10
address termination signals,
8-15
address transfer attribute signals,
8-11
address transfer signals,
8-9
,
9-15
A
n
,
8-9
AP
n
,
8-10
ARTRY,
8-15
,
9-27