Chapter 5. Memory Management
5-3
MMU Overview
The MPC7400 processor also provides the following features that are not required by the
PowerPC architecture:
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Separate translation lookaside buffers (TLBs)The 128-entry, two-way
set-associative ITLBs and DTLBs keep recently-used page address translations
on-chip.
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Table search operations performed in hardwareThe 52-bit virtual address is
formed and the MMU attempts to fetch the PTE, which contains the physical
address, from the appropriate TLB on-chip. If the translation is not found in a TLB
(that is, a TLB miss occurs), the hardware performs a table search operation (using
a hashing function) to search for the PTE.
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TLB invalidationThe MPC7400 implements the optional TLB Invalidate Entry
(
tlbie
) and TLB Synchronize (
tlbsync
) instructions, which can be used to invalidate
TLB entries. For more information on the
tlbie
and
tlbsync
instructions, see
Section 5.4.3.2, òTLB Invalidation.ó
Table 5-1 summarizes the MPC7400 MMU features, including those deTned by the
PowerPC architecture (OEA) for 32-bit processors and those speciTc to the MPC7400.
Table 5-1. MMU Feature Summary
Feature Category
Architecturally DeTned/
MPC7400-SpeciTc
Feature
Address ranges
Architecturally deTned
2
32
bytes of effective address
2
52
bytes of virtual address
2
32
bytes of physical address
Page size
Architecturally deTned
4 Kbytes
Segment size
Architecturally deTned
256 Mbytes
Block address
translation
Architecturally deTned
Range of 128 KbyteD256 Mbyte sizes
Implemented with IBAT and DBAT registers in BAT array
Memory protection
Architecturally deTned
Segments selectable as no-execute
Pages selectable as user/supervisor and read-only or guarded
Blocks selectable as user/supervisor and read-only or guarded
Page history
Architecturally deTned
Referenced and changed bits deTned and maintained
Page address
translation
Architecturally deTned
Translations stored as PTEs in hashed page tables in memory
Page table size determined by mask in SDR1 register
TLBs
Architecturally deTned
Instructions for maintaining TLBs (
tlbie
and
tlbsync
instructions
in MPC7400)
MPC7400-speciTc
128-entry, two-way set associative ITLB
128-entry, two-way set associative DTLB
LRU replacement algorithm