Chapter 2. Programming Model
2-61
Instruction Set Summary
Encodings for the MPC7400-speciTc SPRs are listed in Table 2-46.
SDR1
25
00000
11001
Supervisor (OEA)
Both
SPRG0
272
01000
10000
Supervisor (OEA)
Both
SPRG1
273
01000
10001
Supervisor (OEA)
Both
SPRG2
274
01000
10010
Supervisor (OEA)
Both
SPRG3
275
01000
10011
Supervisor (OEA)
Both
SRR0
26
00000
11010
Supervisor (OEA)
Both
SRR1
27
00000
11011
Supervisor (OEA)
Both
TBL
2
268
01000
01100
Supervisor (OEA)
mtspr
284
01000
11100
Supervisor (OEA)
mtspr
TBU
2
269
01000
01101
Supervisor (OEA)
mtspr
285
01000
11101
Supervisor (OEA)
mtspr
VRSAVE
256
01000
00000
User (AltiVec/UISA)
Both
XER
1
00000
00001
User (UISA)
Both
1
The order of the two 5-bit halves of the SPR number is reversed compared with actual instruction coding. For
mtspr
and
mfspr
instructions, the SPR number coded in assembly language does not appear directly as a
10-bit binary number in the instruction. The number coded is split into two 5-bit halves that are reversed in
the instruction, with the high-order Tve bits appearing in bits 16D20 of the instruction and the low-order Tve
bits in bits 11D15.
The TB registers are referred to as TBRs rather than SPRs and can be written to using the
mtspr
instruction
in supervisor mode and the TBR numbers here. The TB registers can be read in user mode using either the
mftb
or
mtspr
instruction and specifying TBR 268 for TBL and TBR 269 for TBU.
2
Table 2-46. SPR Encodings for MPC7400-Defined Registers (mfspr)
Register
Name
SPR
1
Access
mfspr/mtspr
Decimal
spr[5D9]
spr[0D4]
BAMR
951
11101
10110
Supervisor
Both
DABR
1013
11111
10101
User
Both
HID0
1008
11111
10000
Supervisor
Both
HID1
1009
11111
10001
Supervisor
Both
IABR
1010
11111
10010
Supervisor
Both
ICTC
1019
11111
11011
Supervisor
Both
L2CR
1017
11111
11001
Supervisor
Both
MMCR0
952
11101
11000
Supervisor
Both
MMCR1
956
11101
11100
Supervisor
Both
MMCR2
944
11101
10000
Supervisor
Both
Table 2-45. PowerPC SPR Encodings (Continued)
Register Name
SPR
1
Access
mfspr/mtspr
Decimal
spr[5D9]
spr[0D4]