ILLUSTRATIONS
Figure
Number
Title
Page
Number
Illustrations
xxvii
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
7-1
7-2
7-3
8-1
8-2
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
Pipelined Execution Unit..............................................................................................6-4
Superscalar/Pipeline Diagram.......................................................................................6-5
MPC7400 Microprocessor Pipeline Stages ..................................................................6-8
Instruction Flow Diagram...........................................................................................6-11
Instruction TimingCache Hit..................................................................................6-13
Instruction TimingCache Miss................................................................................6-16
Data L1 Load Hit (No Stalls)......................................................................................6-17
Data L1 Store Hit (No Stalls)......................................................................................6-17
Data L1 Load Miss, L2 Hit (No Stalls).......................................................................6-18
Data L1 Load Miss, L2 Miss, BIU Fetch....................................................................6-19
Branch Folding............................................................................................................6-23
Removal of Fall-Through Branch Instruction.............................................................6-24
Branch Completion.....................................................................................................6-25
Branch Instruction Timing..........................................................................................6-28
Data Dependencies in Non-Java Mode.......................................................................6-34
Data Forwarding in Java Mode...................................................................................6-35
Vector Registers (VRs).................................................................................................7-2
Vector Status and Control Register (VSCR) ................................................................7-3
Vector Save/Restore Register (VRSAVE)....................................................................7-4
60x Bus Signal Groups.................................................................................................8-7
MPX Bus Signal Groups.............................................................................................8-26
MPC7400 Microprocessor Block Diagram ..................................................................9-5
Timing Diagram Legend...............................................................................................9-8
Overlapping Tenures on the MPC7400 Bus for a Single-Beat Transfer......................9-9
Address Bus Arbitration .............................................................................................9-12
Address Bus Arbitration Showing Bus Parking..........................................................9-14
Address Bus Transfer..................................................................................................9-15
Snooped Address Cycle with ARTRY........................................................................9-23
Data Bus Arbitration...................................................................................................9-24
Normal Single-Beat Read Termination ......................................................................9-28
Normal Single-Beat Write Termination......................................................................9-28
Normal Burst Transaction...........................................................................................9-29
Read Burst with TA Wait States.................................................................................9-29
Fastest Single-Beat Reads...........................................................................................9-32
Fastest Single-Beat Writes..........................................................................................9-33
Single-Beat Reads Showing Data-Delay Controls .....................................................9-34