Chapter 4. Exceptions
4-23
Exception DeTnitions
When a decrementer exception is taken, instruction fetching resumes at offset 0x00900
from the physical base address indicated by MSR[IP].
4.6.10 System Call Exception (0x00C00)
A system call exception occurs when a System Call (
sc
) instruction is executed. In the
MPC7400, the system call exception is implemented as it is deTned in the PowerPC
architecture. Register settings for this exception are described in Chapter 6, òExceptions,ó
in
The Programming Environments Manual.
When a system call exception is taken, instruction fetching resumes at offset 0x00C00 from
the physical base address indicated by MSR[IP].
4.6.11 Trace Exception (0x00D00)
The trace exception is taken if MSR[SE] = 1 or if MSR[BE] = 1 and the currently
completing instruction is a branch. Each instruction considered during trace mode
completes before a trace exception is taken. Register settings for this exception are
described in Chapter 6, òExceptions,ó in
The Programming Environments Manual.
Implementation Note
The MPC7400 processor diverges from the PowerPC architecture
in that it does not take trace exceptions on the
isync
instruction.
When a trace exception is taken, instruction fetching resumes as offset 0x00D00 from the
base address indicated by MSR[IP].
4.6.12 Floating-Point Assist Exception (0x00E00)
The optional oating-point assist exception deTned by the PowerPC architecture is not
implemented in the MPC7400.
4.6.13 Performance Monitor Interrupt (0x00F00)
The MPC7400 microprocessor provides a performance monitor facility to monitor and
count predeTned events such as processor clocks, misses in either the instruction cache or
the data cache, instructions dispatched to a particular execution unit, mispredicted
branches, and other occurrences. The count of such events can be used to trigger the
performance monitor exception. The performance monitor facility is not deTned by the
PowerPC architecture.