2-84
MPC7400 RISC Microprocessor Users Manual
AltiVec VEA Instructions
number of complete bytes by which to shift and are used by
vslo
and
vsro
; the low-order 3
bits give the number of remaining bits by which to shift and are used by
vsl
and
vsr
.
Table 2-78 describes the vector shift instructions.
2.5.5.8 Vector Status and Control Register Instructions
Table 2-79 summarizes the instructions for reading from or writing to the AltiVec status
and control register (VSCR), described in Section 7.1.1.5, òVector Save/Restore Register
(VRSAVE).ó
2.6 AltiVec VEA Instructions
The PowerPC virtual environment architecture (VEA) describes the semantics of the
memory model that can be assumed by software processes, and includes descriptions of the
cache model, cache-control instructions, address aliasing, and other related issues.
Implementations that conform to the VEA also adhere to the UISA, but may not necessarily
adhere to the OEA. For further details see Chapter 4, òAddressing Mode and Instruction Set
Summary,ó in
The Programming Environments Manual.
This section describes the additional instructions that are provided by the AltiVec ISA for
the VEA.
2.6.1 AltiVec Vector Memory Control InstructionsVEA
Memory control instructions include the following types:
¥
¥
¥
¥
Cache management instructions (user-level and supervisor-level)
Segment register manipulation instructions
Segment lookaside buffer management instructions
Translation lookaside buffer (TLB) management instructions
Table 2-78. Vector Shift Instructions
Name
Mnemonic
Syntax
Vector Shift Left
vsl
v
D
,v
A
,v
B
Vector Shift Right
vsr
v
D
,v
A
,v
B
Vector Shift Left Double by Octet Immediate
vsldoi
v
D
,v
A
,v
B,SH
Vector Shift Left by Octet
vslo
v
D
,v
A
,v
B
Vector Shift Right by Octet
vsro
v
D
,v
A
,v
B
Table 2-79. Move to/from VSCR Register Instructions
Name
Mnemonic
Syntax
Move to AltiVec Status and Control Register
mtvscr
v
B
Move from AltiVec Status and Control Register
mfvscr
v
B