
9-30
MPC7400 RISC Microprocessor Users Manual
60x Data Bus Tenure
TEA, but to the instruction about to be executed (perhaps several instructions later). Also
note that assertion of TEA does not invalidate data entering the GPR or the cache.
Additionally, the address corresponding to the access that caused TEA to be asserted is not
latched by the MPC7400. To recover, the exception handler must determine and remedy the
cause of the TEA, or the MPC7400 must be reset; therefore, this function should only be
used to indicate fatal system conditions to the processor (such as parity or uncorrectable
ECC errors).
After the MPC7400 has committed to run a transaction, that transaction must eventually
complete. Address retry causes the transaction to be restarted; TA wait states delay
termination of individual data beats. Eventually, however, the system must either terminate
the transaction or assert the TEA signal. For this reason, care must be taken to check for the
end of physical memory and the location of certain system facilities to avoid memory
accesses that result in the assertion of TEA.
Note that TEA generates a machine check exception depending on MSR[ME]. Clearing
the machine check exception enable control bits leads to a true checkstop condition
(instruction execution halted and processor clock stopped).
9.4.3.3 No-DRTRY Mode
The MPC7400 disallows the use of the data retry function provided by some 60x
processors, and no-DRTRY mode is always selected. The no-DRTRY mode provides
higher performance because it allows the forwarding of data during load operations to the
internal CPU one bus cycle sooner than in the standard 60x bus protocol that implements
DRTRY.
Because the MPC7400 always operates in no-DRTRY mode, the assertion of ARTRY by a
snooping device must occur prior to or coincident with the Trst assertion of TA to the
MPC7400; assertion of ARTRY must never occur on the cycle after the Trst assertion of
TA.
9.4.4 Using Data Bus Write Only (DBWO)
The MPC7400 supports split-bus pipelined transactions and a limited out-of-order
capability for its own pipelined transactions through the data bus write only (DBWO)
signal. When recognized on the clock of a qualiTed DBG, the assertion of DBWO directs
the MPC7400 to perform the next pending data write tenure (if any), even if a pending read
tenure would have normally been performed because of address pipelining. The DBWO
signal does not change the order of write tenures with respect to other write tenures from
the same MPC7400. It only allows that a write tenure be performed ahead of a pending read
tenure from the same MPC7400.
Note that DBWO can be asserted if no data bus read is pending, but it has no effect on write
ordering.