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MPC7400 RISC Microprocessor Users Manual
Memory Segment Model
Figure 5-8. tlbie Instruction Execution and Bus Snooping Flow
The execution of the
tlbie
instruction is performed as if the TLBIE operation was snooped
from the system bus by loading a single-entry TLBIQ that contains EA[14:19] and a valid
bit. When the invalidation of the TLBs is complete, the TLBIQ is invalidated. Also, all valid
queues in the machine that contain a previously translated address (physical address) are
internally marked because these queues could contain references to addresses from the just
invalidated TLB entries. These references propagate through to completion, but are marked
for the purposes of synchronizing multiple TLB invalidations in multiple processors. See
Section 5.4.3.2.2, òtlbsync Instruction,ó for more information on the use of these internal
marks.
When another processor on the system bus performs a TLBIE address-only transaction, the
MPC7400 snoops the transaction and checks the status of its internal TLBIQ. If the TLBIQ
is valid (that is, the processor is in the process of performing a TLB invalidation), it causes
a retry of the transaction until the TLBIQ empties. If the TLBIQ is invalid and the
transaction is not retried by any other processor, the MPC7400 loads the TLBIQ with
EA[14:19] and sets the TLBIQ valid bit. This causes the MPC7400 to invalidate the four
TLBIE transaction
TT[0:4]
11000
Initiate TLBIE transaction on bus
A[14:19] EA[14:19]
TT[0:4] 11000
Retry the transaction
MPC7400 Bus
Snooping Logic
Otherwise
tlbie
end of
tlbie
ow
no other retry signaled;
transaction completes
Continue with bus
snooping and
instruction execution
All pending accesses with previously
translated addresses
Mark
Invalidate the
2 indexed ITLB entries and the
2 indexed DTLB entries
Pending accesses with
previously translated
addresses
propagate through
As each access completes, its
associated mark is cleared
transaction is retried
by another processor
Otherwise
Otherwise
TLBIQ[V] = 1
TLBIQ
A[14:19]
TLBIQ[V]
1
TLBIQ[V]
0