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MPC7400 RISC Microprocessor Users Manual
Organization
provides an overview of how the PowerPC architecture deTnes the register set,
operand conventions, addressing modes, instruction set, cache model, exception
model, and memory management model.
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Chapter 2, òProgramming Model,ó is useful for software engineers who need to
understand the MPC7400-speciTc registers, operand conventions, and details
regarding how PowerPC instructions are implemented on the MPC7400.
Instructions are organized by function.
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Chapter 3, òL1 and L2 Cache Operation,ó discusses the cache and memory model as
implemented on the MPC7400.
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Chapter 4, òExceptions,ó describes the exception model deTned in the PowerPC
OEA and the speciTc exception model implemented on the MPC7400.
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Chapter 5, òMemory Management,ó describes the MPC7400s implementation of
the memory management unit speciTcations provided by the PowerPC OEA for
PowerPC processors.
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Chapter 6, òInstruction Timing,ó provides information about latencies, interlocks,
special situations, and various conditions to help make programming more efTcient.
This chapter is of special interest to software engineers and system designers.
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Chapter 7, òThe AltiVec Technology Implementation,ó summarizes the features and
functionality provided by the implementation of the AltiVec technology.
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Chapter 8, òSignal Descriptions,ó provides descriptions of individual signals of the
MPC7400.
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Chapter 9, òSystem Interface Operation,ó describes signal timings for various
operations. It also provides information for interfacing to the MPC7400.
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Chapter 10, òPower and Thermal Management,ó provides information about power
saving and thermal management modes for the MPC7400.
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Chapter 11, òPerformance Monitor,ó describes the operation of the performance
monitor diagnostic tool incorporated in the MPC7400.
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Appendix A, òMPC7400 Instruction Set Listings,ó lists all the PowerPCa
instructions while indicating those instructions that are not implemented by the
MPC7400; it also includes the instructions that are speciTc to the MPC7400.
Instructions are grouped according to mnemonic, opcode, function, and form. Also
included is a quick reference table that contains general information, such as the
architecture level, privilege level, and form, and indicates if the instruction is 64-bit
and optional.
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Appendix B, òInstructions Not Implemented,ó provides a list of the 32-bit and 64-bit
PowerPC instructions that are not implemented in the MPC7400.
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This manual also includes a glossary and an index.