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MPC7400 RISC Microprocessor Users Manual
Differences between the MPC7400 and the MPC750
L2 cache
The MPC7400 has twice as many on-chip L2 tags per way (8192) than the MPC750 and can support
twice the L2 cache size (up to 2 Mbyte). The sectoring conTguration is differs as follows:
Assigning fewer sectors per tag uses the cache more efTciently.
The MPC7400 and MPC750 also have different cache reload policies. On the MPC750, an L1 cache miss
that also misses in the L2 causes a reload from the bus to both L1 and L2. On the MPC7400, misses to
the L1 instruction cache behave the same way, but misses to the L1 data cache cause data to be
reloaded into the L1 only. Thus, with respect to the L1 data cache, the L2 holds only blocks that are cast
out; it acts as a giant victim cache for the L1 data cache. This improves performance because the data is
duplicated in the L1 data cache and L2 less often.
60x bus/
MPX bus
The MPC7400 supports the 60x bus used by the MPC750, but it also supports a new bus (MPX bus). It
implements a 5-state cache-coherency protocol (MERSI) and the MESI and MEI subsets. This provides
better hardware support of multiprocessing.
For example, the MPX bus supports data intervention. On the 60x bus, if one processor does a read of
data that is marked modiTed in another processors cache, the transaction is retried and the data is
pushed to memory, after which the transaction is restarted. The MPX bus allows data to be forwarded
directly to the requesting processor from the processor that has it cached. (The MPC7400 also supports
intervention for data marked exclusive and shared.)
The MPC7400 supports up to seven simultaneous transactions on the 60x or MPX bus interface (one in
progress and six pending); the MPC750 supports only two.
Table 1-7. Differences between the MPC7400 and the MPC750 (Continued)
Feature
Difference
MPC750
MPC7400
1 Mbyte
512 Kbyte
256 Kbyte
4 sectors/tag
2 sectors/tag
2 sectors/tag
2 Mbyte
1 Mbyte
512 Kbyte
4 sectors/tag
2 sectors/tag
1 sector/tag