6-26
MPC7400 RISC Microprocessor Users Manual
Execution Unit Timings
The number of instructions that can be executed after the issue of a predicted branch
instruction is limited by the fact that no instruction executed after a predicted branch may
actually update the register Tles or memory until the branch is completed. That is,
instructions may be issued and executed, but cannot reach the write-back stage in the
completion unit. When an instruction following a predicted branch completes execution, it
does not write back its results to the architected registers, instead, it stalls in the CQ. Of
course, when the CQ is full, no additional instructions can be dispatched, even if an
execution unit is idle.
In the case of a misprediction, the MPC7400 can easily redirect its machine state because
the programming model has not been updated. When a branch is mispredicted, all
instructions that were dispatched after the predicted branch instruction are ushed from the
CQ and any results are ushed from the rename registers.
The BTIC is a cache of recently used branch target instructions. If the search for the branch
target hits in the cache, the Trst one or two branch instructions is available in the instruction
queue on the next cycle (shown in Figure 6-5). Two instructions are fetched on a BTIC hit,
unless the branch target is the last instruction in a cache block, in which case one instruction
is fetched.
In some situations, an instruction sequence creates dependencies that keep a branch
instruction from being resolved immediately, thereby delaying execution of the subsequent
instruction stream based on the predicted outcome of the branch instruction. The instruction
sequences and the resulting action of the branch instruction are described as follows:
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An
mtspr
(LR) followed by a
bclr
Fetching stops and the branch waits for the
mtspr
to execute.
An
mtspr
(CTR) followed by a
bcctr
Fetching stops and the branch waits for the
mtspr
to execute.
An
mtspr
(CTR) followed by a
bc
(CTR decrement)Fetching stops and the branch
waits for the
mtspr
to execute.
A third
bc
(based-on-CR) is encountered while there are two unresolved
bc
(based-on-CR). The third
bc
(based-on-CR) is not executed and fetching stops
until one of the previous
bc
(based-on-CR) is resolved. (Note that branch conditions
can be a function of the CTR and the CR; if the CTR condition is sufTcient to resolve
the branch, then a CR-dependency is ignored.)
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