Chapter 6. Instruction Timing
6-1
Chapter 6
Instruction Timing
This chapter describes how the MPC7400 microprocessor fetches, dispatches, and executes
instructions and how it reports the results of instruction execution. It gives detailed
descriptions of how the MPC7400 execution units work and how those units interact with
other parts of the processor, such as the instruction fetching mechanism, register Tles, and
caches. It gives examples of instruction sequences, showing potential bottlenecks and how
to minimize their effects. Finally, it includes tables that identify the unit that executes each
instruction implemented on the MPC7400, the latency for each instruction, and other
information that is useful for the assembly language programmer.
AltiVec Technology and Instruction Timing
The AltiVec functionality in the MPC7400 affects instruction timing in the following ways:
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Additional execution units are provided for handling AltiVec permute (VPU) and
ALU instructions (VALU)
The VALU consists of three independent execution units:
Vector simple integer unit (VSIU). See Section 6.4.8.2.1, òVector Simple Integer
Unit (VSIU) Execution Timing.ó
Vector complex integer unit (VCIU). See Section 6.4.8.2.2, òVector Complex
Integer Unit (VCIU) Execution Timing.ó
Vector oating-point unit (VFPU). See Section 6.4.8.2.3, òVector Floating-Point
Unit (VFPU) Execution Timing.ó
The AltiVec technology deTnes data streaming instruction that allows automated
loading of data for nonspeculative accesses. These instructions can be identiTed as
either static (likely to be reused) or transient (unlikely to be reused). See
Section 7.1.2, òAltiVec Instruction Set.ó
The AltiVec technology deTnes load and store instructions that can be identiTed as
least-recently-used, in order to free up data with low likelihood for reuse. See
Section 6.4.7.1, òLRU Instructions.ó
Latencies for AltiVec instructions are listed in Table 6-9
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