11-14
MPC7400 RISC Microprocessor Users Manual
Event Selection
11 (000_1011)
Load miss latency
over threshold
Counts the times a load that misses in the L1 data cache needs more than
the threshold number of cycles to write back to the rename registers. The
cycle count compared to the threshold value represents the number of
cycles starting with allocation in the load-fold-queue or data reload table.
Note that MMCR2[0] determines whether the value in the MMCR0 threshold
Teld is multiplied by 2 or 32.
Note that misaligned loads require two cache accesses. The miss latency
threshold is measured from the Trst access that misses up until both
halves
of load are written to the rename registers. Load multiple/string instructions
can generate many separate cache accesses. For these loads, the
threshold is measured starting with the Trst access that misses until the
entire multiple or string operation is complete.
12 (000_1100)
Unresolved branches
Counts branches that are unresolved when processed
13 (000_1101)
Dispatch stall due to
speculative branches
Counts cycles the dispatcher halts due to a second unresolved branch in
the instruction stream
14 (000_1110)
mfvscr
synchronization
Count cycles the VALU had a valid
mfvscr
dispatch but could not execute it
because it is not at the bottom of the completion queue
15 (000_1111)
mtvscr
instructions
completed
Counts completed
mtvscr
instructions
16 (001_0000)
mtvrsave
instructions
completed
Counts completed
mtvrsave
instructions
17 (001_0001)
VSCR[SAT] set
Counts whenever VSCR[SAT] goes from 0 to 1
18 (001_0010)
Clean L1 castouts to
L2
Counts times the L1 casts out clean data to the L2.
19 (001_0011)
Instruction table
search latency over
threshold
Counts when an instruction table search requires more than the threshold
number of cycles to complete. Includes searches that do not Tnd a matching
PTE. Note that MMCR2[0] determines whether the value in the MMCR0
threshold Teld is multiplied by 2 or 32.
20 (001_0100)
Data table search
latency over threshold
Counts when a data table search requires more than the threshold number
of cycles to complete. Includes searches that do not Tnd a matching PTE
and searches caused by
dst
x
instructions. Note that MMCR2[0] determines
whether the value in the MMCR0 threshold Teld is multiplied by 2 or 32.
21 (001_0101)
Completed stores
Counts all store instructions completed.
22 (001_0110)
dL1 load hit
Counts each data L1 cache load hit; misaligned load accesses are counted
separately. Does not include MMU table search lookups.
23 (001_0111)
dL1 store hit
Counts write-back store hit attempts that successfully hit on the L1 data
cache. Does not count if store hit on shared cache block.
24 (001_1000)
dL1 hits
Counts data L1 load, store, and touch hits
25 (001_1001)
L2 tag lookup
Counts once per each L2 tag lookup. Does not include snoop look-ups.
26 (001_1010)
L2 tag accesses
Counts L2 tag accesses, including L2 tag lookups, writes, snoop look-ups,
and snoop writes
27 (001_1011)
BIU non-ARTRYed
data TS assertions
Counts read and write transactions performed on the system interface.
Does not count address only transaction types.
28 (001_1100)
BIU read cycle of 8
bytes or fewer
Counts TA assertions for 64-bit reads. Anything less than 8 bytes counts as
8.
Table 11-8. PMC1 EventsMMCR0[19D25] Select Encodings (Continued)
Number
Event
Description