Chapter 11. Performance Monitor
11-1
Chapter 11
Performance Monitor
The PowerPC architecture deTnes an optional performance monitor facility that provides
the ability to monitor and count predeTned events such as processor clocks, misses in the
instruction cache, data cache, or L2 cache, types of instructions dispatched, mispredicted
branches, and other occurrences. The count of such events (which may be an
approximation) can be used to trigger the performance monitor exception. Note that some
earlier PowerPC processors implemented the performance monitor facility before it was
deTned by the PowerPC architecture.
The performance monitor can be used for the following:
¥
To increase system performance with efTcient software, especially in a
multiprocessing systemMemory hierarchy behavior may be monitored and
studied in order to develop algorithms that schedule tasks (and perhaps partition
them) and that structure and distribute data optimally.
To characterize processorsSome environments may not be easily characterized by
a benchmark or trace.
To help system developers bring up and debug their systems
¥
¥
AltiVec Technology and the Performance Monitor
The AltiVec technology features do not affect the basic implementation of the performance
monitor. The performance monitor does provide the ability to monitor the following
AltiVec operations:
¥
Maintains individual counts of instructions executed by the AltiVec execution units,
the vector simple integer execution unit (VSIU), vector complex integer execution
unit (VCIU), vector oating-point unit (VFPU), and vector permute unit (VPU)
Counts AltiVec load instructions completed
Maintains individual counts of cycles during which the VSIU, VCIU, VFPU, and
VPU had a valid dispatch but invalid operands
Counts VFPU traps that can be generated in Java mode
Counts
mtvscr
and
mtvrsave
instructions
Counts settings of the VSCR saturate bit
Counts completions of
dss
and
dssall
instructions
¥
¥
¥
¥
¥
¥