Chapter 2. Programming Model
2-17
The MPC7400 Processor Register Set
6
FCECE
Freeze counters on enabled condition or event.
0 The PMCs are incremented (if permitted by other MMCR bits).
1 The PMCs are incremented (if permitted by other MMCR bits) until an enabled
condition or event occurs when MMCR0[TRIGGER] = 0, at which time MMCR0[FC]
is set If the enabled condition or event occurs when MMCR0[TRIGGER] = 1,
FCECE is treated as if it were 0.
The use of the trigger and freeze counter conditions depends on the enabled
conditions and events described in Section 11.2, òPerformance Monitor Interrupt.ó
7D8
TBSEL
Time base selector. Selects the time base bit that can cause a time base transition
event (the event occurs when the selected bit changes from 0 to 1).
00
TB[63] (TBL[31])
01
TB[55] (TBL[23])
10
TB[51] (TBL[19])
11
TB[47] (TBL[15])
Time base transition events can be used to periodically collect information about
processor activity. In multiprocessor systems in which TB registers are synchronized
among processors, time base transition events can be used to correlate the
performance monitor data obtained by the several processors. For this use, software
must specify the same TBSEL value for all the processors in the system. Because the
time-base frequency is implementation-dependent, software should invoke a system
service program to obtain the frequency before choosing a value for TBSEL.
9
TBEE
Time base event enable.
0 Time-base transition events are disabled.
1 Time-base transition events are enabled. A time-base transition is signaled to the
performance monitor if the TB bit speciTed in MMCR0[TBSEL] changes from 0 to 1.
Time-base transition events can be used to freeze the counters (MMCR0[FCECE]),
trigger the counters (MMCR0[TRIGGER]), or signal an exception (MMCR0[PMXE]).
Changing the bits speciTed in MMCR0[TBSEL] while MMCR0[TBEE] is enabled may
cause a false 0 to 1 transition that signals the speciTed action (freeze, trigger, or
exception) to occur immediately.
10D15 THRESHOLD
Threshold. Contains a threshold value, which is a value such that only events that
exceed the value are counted (PMC1 events 11, 19, and 20).
By varying the threshold value, software can obtain a proTle of the characteristics of
the events subject to the threshold. For example, if PMC1 counts cache misses for
which the duration exceeds the threshold value, software can obtain the distribution of
cache miss durations for a given program by monitoring the program repeatedly using
a different threshold value each time.
Note that MMCR2[THRESHMULT] chooses whether this value is multiplied by 2 or 32.
16
PMC1CE
PMC1 condition enable. Controls whether counter negative conditions due to a
negative value in PMC1 are enabled.
0 Counter negative conditions for PMC1 are disabled.
1 Counter negative conditions for PMC1 are enabled. These events can be used to
freeze the counters (MMCR0[FCECE]), trigger the counters (MMCR0[TRIGGER]),
or signal an exception (MMCR0[PMXE]).
17
PMCjCE
PMCj condition enable. Controls whether counter negative conditions due to a
negative value in any PMCj (that is, in any PMC except PMC1) are enabled.
0 Counter negative conditions for all PMCjs are disabled.
1 Counter negative conditions for all PMCjs are enabled. These events can be used to
freeze the counters (MMCR0[FCECE]), trigger the counters (MMCR0[TRIGGER]),
or signal an exception (MMCR0[PMXE]).
Table 2-7. MMCR0 Field Descriptions (Continued)
Bits
Name
Description