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xvi
MPC7400 RISC Microprocessor Users Manual
CONTENTS
Paragraph
Number
Title
Page
Number
8.2.4.4
8.2.4.5
8.2.4.5.1
8.2.4.5.2
8.2.4.6
8.2.4.7
8.2.5
8.2.5.1
8.2.5.2
8.2.5.2.1
8.2.5.2.2
8.2.5.3
8.2.5.3.1
8.2.5.3.2
8.2.6
8.2.6.1
8.2.6.2
8.2.6.3
8.2.7
8.2.7.1
8.2.7.1.1
8.2.7.1.2
8.2.7.2
8.2.7.2.1
8.2.7.2.2
8.2.8
8.2.8.1
8.2.8.2
8.3
8.3.1
8.3.1.1
8.3.1.2
8.3.1.3
8.3.1.4
8.3.1.5
8.3.1.6
8.3.2
8.3.3
8.4
8.4.1
8.4.2
8.4.2.1
8.4.2.2
Transfer Size (TSIZ[0:2])Output.......................................................... 8-13
Global (
GBL
)............................................................................................ 8-13
Global (
GBL
)Output......................................................................... 8-13
Global (
GBL
)Input ........................................................................... 8-14
Write-Through (
WT
)Output................................................................. 8-14
Cache Inhibit (
CI
)Output...................................................................... 8-14
Address Transfer Termination Signals......................................................... 8-15
Address Acknowledge (
AACK
)Input.................................................. 8-15
Address Retry (
ARTRY
).......................................................................... 8-15
Address Retry (
ARTRY
)Output....................................................... 8-15
Address Retry (
ARTRY
)Input.......................................................... 8-16
Shared (
SHD
)........................................................................................... 8-17
Shared (
SHD
)Output........................................................................ 8-17
Shared (
SHD
)Input........................................................................... 8-17
Data Bus Arbitration Signals........................................................................ 8-17
Data Bus Grant (
DBG
)Input................................................................. 8-18
Data Bus Write Only (
DBWO
)Input.................................................... 8-18
Data Bus Busy (
DBB
)Output................................................................ 8-19
Data Transfer Signals.................................................................................... 8-19
Data Bus (DH[0:31], DL[0:31])............................................................... 8-19
Data Bus (DH[0:31], DL[0:31])Output............................................ 8-20
Data Bus (DH[0:31], DL[0:31])Input............................................... 8-20
Data Bus Parity (DP[0:7]) ........................................................................ 8-20
Data Bus Parity (DP[0:7])Output..................................................... 8-20
Data Bus Parity (DP[0:7])Input........................................................ 8-21
Data Transfer Termination Signals............................................................... 8-21
Transfer Acknowledge (
TA
)Input........................................................ 8-21
Transfer Error Acknowledge (
TEA
)Input............................................ 8-22
60x/MPX Bus Protocol Signal Compatibility................................................... 8-22
60x Bus Signals Not in the MPC7400.......................................................... 8-23
Address Bus Busy and Data Bus Busy (ABB and DBB)......................... 8-23
Data Retry (DRTRY)................................................................................ 8-23
Extended Transfer Protocol (XATS)........................................................ 8-23
Transfer Code (TC[0:1])........................................................................... 8-23
Cache Set Element (CSE[0:1])................................................................. 8-23
Address Parity Error and Data Parity Error (APE, DPE)......................... 8-24
60x Signals Multiplexed with New MPX Bus Mode Signals ...................... 8-24
New MPX Bus Mode Signals....................................................................... 8-24
MPX Bus Signal Configuration........................................................................ 8-25
MPX Bus Mode Functional Groupings........................................................ 8-25
MPX Address Bus Arbitration Signals......................................................... 8-26
Bus Request (BR)Output...................................................................... 8-27
Bus Grant (BG)Input ............................................................................ 8-27