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| 型號： | MPC801 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 35K |
| 代理商： | MPC801 |
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MPC801/D
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
PowerQUICC
is a registered trademark of Motorola, Inc.
PowerPC
is a registered trademark of IBM Corp. and is used under license from IBM Corp.
Product Brief
MPC801 Microprocessor
MPC801
1996 Motorola, Inc. All Rights Reserved.
Microprocessor and Memory
Technologies Group
SEMICONDUCTOR PRODUCT INFORMATION
The MPC801 is derived from the MPC860 PowerQUICC
combination that can be used in a variety of controller applications. It is a low-cost, general-purpose embedded
PowerPC
microprocessor that provides effective price/performance across a wide range of applications. The
MPC801, like the MPC860, combines a high-performance PowerPC core with a multifaceted system integration
package.
integrated microprocessor and peripheral
KEY FEATURES
The following is a list of the main features of the MPC801:
Embedded PowerPC core with 52 MIPS at 40 MHz (using Dhrystone 2.1)
Single-issue, 32-bit version of the embedded PowerPC core (fully compatible with the
Instruction Set Architecture (Book I)
) with 32
PowerPC
User
×
32-bit fixed-point registers
— Embedded PowerPC core performs branch folding and branch prediction with conditional
pre-fetch, but without conditional execution
— 1K data cache and 2K instruction cache
— Instruction and data caches are two way, set-associative, physical address, 4 word line burst,
least recently used (LRU) replacement, lockable online granularity
— MMUs with 8-entry TLB, fully associative instruction and data TLBs
— MMUs support 4K, 16K, 512K and 8M page sizes; 16 virtual address spaces and
16 protection groups
— Advanced on-chip emulation debug mode
Up to 32-bit data bus (dynamic bus sizing for 8,16, and 32 bits controlled by memory controller)
26 external address lines
Complete static design (0–40 MHz operation)
Memory controller (eight banks)
— Contains complete dynamic random-access memory (DRAM) controller
— Each bank can be a chip-select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM single in-line memory modules (SIMMs), static random-access
memory (SRAM), electrically programmable read-only memory (EPROM), and FLASH EPROM.
— DRAM controller programmable to support a wide range of sizes and speed DRAM memory.
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32K to 256M)
— Selectable write protection
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| MPC8010 | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:PASSIVE DEVICES - MMSM� Capacitors |
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| MPC8020 | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:PASSIVE DEVICES - MMSM� Capacitors |
| MPC8050 | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:PASSIVE DEVICES - MMSM� Capacitors |
| MPC8100 | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:PASSIVE DEVICES - MMSM� Capacitors |
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