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參數(shù)資料
| 型號(hào)： | MPC801 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 35K |
| 代理商： | MPC801 |
4
MPC801 PRODUCT INFORMATION
MOTOROLA
EMBEDDED POWERPC CORE
The embedded PowerPC core complies with the specifications discussed in
Architecture (Book I)
. The embedded PowerPC core has a fully static design that consists of two functional
blocks—the integer block and load/store block. It executes all integer and load/store operations directly on the
hardware. The core supports integer operations on a 32-bit internal data path with 32-bit arithmetic hardware.
The interface to the internal and external busses is 32 bits.
PowerPC
User Instruction Set
The core uses a two instruction load/store queue, a four instruction prefetch queue, and a six instruction history
buffer. It does branch folding and branch prediction with conditional pre-fetch, but does not support conditional
execution. The core can operate on 32-bit external operands with one bus cycle. The PowerPC integer block
supports 32
×
32-bit fixed-point general-purpose registers and executes one integer instruction per clock cycle.
The embedded PowerPC core is integrated with the MMUs as well with the 2K instruction cache and 1K data
cache. Each MMU provides an 8-entry, fully associative instruction and data TLB, with 4K, 16K, 512K, and 8M
page sizes. It supports 16 virtual address spaces with 16 protection groups. Three special registers are
available as scratch registers to support software tablewalk and update.
The instruction cache is 2K, two way, set associative with physical addressing. It allows single cycle access
on hit with no added latency for miss. It has four words per line supporting burst line fill using least recently
used (LRU) replacement. The cache can be locked on a per line basis for application critical routines. The
cache inhibit mode can be programmed on a per MMU page basis.
The data cache is 1K, two way, set associative with physical addressing. It allows single cycle access on hit
with one added clock latency for miss. It has four words per line, supporting burst line fill using LRU
replacement. The cache can be locked on a per line basis for application critical data. The data cache can be
programmed to support copyback or writethrough via the MMU. The cache inhibit mode can be programmed
on a per MMU page basis. The PowerPC core, together with its instruction and data caches, delivers
approximately 52 MIPS at 40 MHz using Dhrystone 2.1.
The PowerPC core contains an improved debug interface that provides superior debug capabilities without
causing any degradation in the speed of operation. This interface supports six watchpoint pins that are used
to detect software events. Internally, it has eight comparators, four of which operate on the effective address
of the address bus. The remaining four comparators are split. Two comparators operate on the effective
address of the data address bus and two operate on the data bus. The core can compare using the =,
and > conditions to generate watchpoints. Then each watchpoint can generate a breakpoint that can be
programmed to trigger after a certain number of events.
≠
, <,
SYSTEM INTERFACE UNIT
The system interface unit (SIU) on the MPC801 integrates general-purpose features useful in almost any 32-bit
processor system, thus enhancing the performance provided by the system integration module on the
MC68360 QUICC device. Multiple bus port sizes are supported and bus sizing allows 8-, 16-, and 32-bit
peripherals and memory to exist in the 32-bit system bus mode. Data parity is supported using 4-bit data parity
pins and the parity type can be odd or even. The SIU also contains power management functions, reset control,
decrementer, timebase, and real-time clock.
The memory controller manages memories with a nonmultiplexed address bus (SRAM, SSRAM, EPROM,
flash EPROM, and other peripherals) using the SRAM interface. Using the DRAM interface, the memory
controller also manages memories with a multiplexed address bus (DRAM, SRDRAM, and EDO). Both
submodules support glueless interface to 8-, 16-, and 32-bit wide memories. The memory controller supports
up to eight memory banks and can use address type matching to qualify the memory bank accesses. Each
bank can use either the SRAM or DRAM interface. The memory controller provides four byte enable signals,
one output enable signal, and one boot chip-select available at reset.
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