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參數(shù)資料
| 型號： | MPC801 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 35K |
| 代理商： | MPC801 |
2
MPC801 PRODUCT INFORMATION
MOTOROLA
System integration unit
— Bus monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— On-chip bus arbitration logic
— PowerPC decrementer
— PowerPC timebase
— RTC
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Interrupts
— Eight external interrupt request (IRQ0-7) lines
— Internal interrupt sources: SPI, I2C, UART1, UART2, TB, PIT, and RTC
UART support
— Two UARTs
— Standard baud rates of 300 bps to 115.2 kbps with 16
— External 1
×
clock for high-speed synchronous communication
— Flexible 5-wire serial interface
— Direct support of IrDA physical layer protocol
— 8-byte FIFOs for transmit and receive
— Programmable data format
— Seven or eight data bits plus parity
— Odd, even, no parity, or force parity error
— One or two stop bits
— Programmable channel modes (normal and local loopback)
— Parity, framing, and overrun error detection
— Generation and detection of break
— Robust receiver data sampling with noise filtering
— Eight maskable interrupts
— Low-power idle mode
×
sample clock
I
2
C support
— Two-wire interface (SDA and SCL)
— Full-duplex operation
— Master or slave I
— Multi-master environment support
— Clock rate support at a maximum of 520 KHz (assuming a 25-MHz system clock)
— Local loopback capability for testing
2
C mode support
SPI support
— Four-wire interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL)
— Full-duplex operation
— 8- and 1-bit data character operation
— Back-to-back character transmission and reception support
— Master or slave SPI modes support
— Multi-master environment support
— Clock rates support at a maximum of 6.25 MHz in master mode and 12.5 MHz in slave mode
(assuming a 25-MHz system clock)
— Independent programmable baud rate generator
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