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參數資料
| 型號： | MPC801 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數： | 3/8頁 |
| 文件大?。?/td> | 35K |
| 代理商： | MPC801 |
MOTOROLA
MPC801 PRODUCT INFORMATION
3
— Programmable clock phase and polarity
— Open-drain output pins support multi-master configuration
— Local loopback capability for testing
Low-power support
— Full on–all units fully powered
— Doze–core functional units disabled except timebase decrementer, PLL, memory controller, and
RTC in low-power standby
— Sleep–all units disabled except RTC and PIT (PLL active for fast wake-up)
— Deep sleep–all units disabled (including PLL), except RTC and PIT
Debug interface
— Eight comparators (four operate on instruction address, two operate on data address, and two
operate on data)
— Supports =
≠
< > conditions
— Each watchpoint can generate a breakpoint internally
3.3 V operation with 5-V TTL compatibility
256-pin ball grid array (BGA) package
The MPC801 is a combination of the embedded PowerPC core and integrated peripherals brought together to
meet the demands of various communications and networking products. The MPC801 is comprised of six
modules that all use the 32-bit internal bus:
Embedded PowerPC core
System integration unit
Two UARTs
I
2
C
SPI
The MPC801 block diagram is illustrated in Figure 1 below.
Figure 1. MPC801 Block Diagram
EMBEDDED
POWERPC
CORE
LOAD/STORE
BUS
INSTRUCTION
BUS
I-CACHE
I-MMU
D-CACHE
D-MMU
SYSTEM
INTERFACE UNIT
BIU
UART
I
2
C
SPI
PIO
UART
MEMORY
CONTROLLER
SYSTEM
FUNCTIONS
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