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參數(shù)資料
| 型號： | MPC801 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 35K |
| 代理商： | MPC801 |
MOTOROLA
MPC801 PRODUCT INFORMATION
5
The SRAM interface provides block sizes that vary between 32K to 64MB. Each bank of memory has 0 to 30
wait states (zero wait state means a two-clock access to external SRAM). The DRAM interface supports 256K,
512K, 1M, 2B, 4M, 8M, 16M, 32M, or 64M memory bank depths for all port sizes. The memory depth can be
defined as 64K and 128K for 8-bit memory or 128M and 256M for 32-bit memory. The DRAM controller
supports page mode access for successive transfers within bursts.
The MPC801 supports a glueless interface to one bank of DRAM, but external buffers are required for
additional memory banks. The refresh unit provides CAS before RAS, a programmable refresh timer, disable
refresh mode, and stacking for seven refresh cycles. The DRAM interface uses a programmable state machine
to support most memory interfaces.
COMMUNICATION CHANNELS A AND B
Each communication channel has a full-duplex universal asynchronous receiver/transmitter (UART). The
operating frequency for each receiver and each transmitter can be selected independently from the baud rate
generator, counter/timer, or external clock. The transmitter accepts parallel data from the CPU, converts it to
a serial bitstream, inserts the appropriate start, stop, and optional parity bits, and then outputs a composite
serial stream of data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this serial
input to parallel format, checks for a start bit, stop bit, parity bit (if any), or break condition, and transfers an
assembled character to the CPU during read operations.
I
2
C CONTROLLER
The I
board. It uses two wires (serial data and serial clock) to carry information between the integrated circuits that
are connected to the bus. The I
C controller consists of transmitter and receiver sections, an independent baud
rate generator, and a control unit. The transmitter and receiver sections use the same clock that is derived from
the I
C controller baud rate generator in master mode and generated externally in slave mode.
2
C controller is a synchronous, multimaster bus that is used to connect several integrated circuits on a
2
2
SPI CONTROLLER
The serial peripheral interface (SPI) is a full-duplex, synchronous, character-oriented channel that supports a
four-wire interface (receive, transmit, clock and slave select). The SPI block consists of transmitter and
receiver sections, an independent baud rate generator, and a control unit. The transmitter and receiver
sections use the same clock that is derived from the SPI baud rate generator in master mode and generated
externally in slave mode. During an SPI transfer, data is simultaneously transmitted and received.
POWER MANAGEMENT
The MPC801 supports a wide range of power management features, including full-on, doze, sleep, deep sleep,
and low-power stop. In full-on mode, the MPC801 processor is fully powered with all internal units operating
at full speed. A gear mode is provided (determined by a clock divider) that allows the operating system to
reduce the operational frequency of the processor. Doze mode disables core functional units (except for the
timebase, decrementer, PLL, memory controller, and RTC). Sleep mode disables everything, except the RTC
and PIT, thus leaving the PLL active for quick wake-up. The deep sleep mode disables the PLL for low-power,
but at the expense of a slower wake-up. Low-power stop disables all logic in the processor (except the
minimum logic required to restart the device) and lowers the power consumption, but it also requires the
longest wake-up time.
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