11-16
MPC7400 RISC Microprocessor Users Manual
Event Selection
11.5.2 PMC2 Events
Bits MMCR0[26D31] specify events associated with PMC2, as shown in Table 11-9.
48 (011_0000)
AltiVec loads
completed
Counts AltiVec load instructions completed (0, 1, or 2 instructions per cycle)
All others
Reserved
Table 11-9. PMC2 EventsMMCR0[26D31] Select Encodings
Number
Event
Description
0 (00_0000)
Nothing
Register counter holds current value
1 (00_0001)
Processor cycles
Counts every processor cycle
2 (00_0010)
Instructions
completed
Counts completed instructions. Does not include folded branches. 0, 1, or 2
instructions per cycle.
3 (00_0011)
TBL bit transitions
Count transitions from 0 to 1 of TBL bits speciTed through MMCR0[TBSEL]
4 (00_0100)
Instructions
dispatched
Counts dispatched instructions (0, 1, or 2 instructions per cycle)
5 (00_0101)
Number of fall
through branches
Counts branches resolved as not taken
6 (00_0110)
ITLB misses
Counts times that a requested address translation was not in the ITLB
7 (00_0111)
VSIU instructions
completed
Counts instructions completed by the VSIU (0, 1, or 2 instructions per cycle)
8 (00_1000)
VCIU wait
Counts cycles for which the VCIU had a valid dispatch but invalid operands
9 (00_1001)
User/supervisor
mode switches
Counts the times MSR[PR] toggles
10 (00_1010)
Reserved loads
Counts completed reserved load instructions
11 (00_1011)
Loads
Counts completed load instructions (0, 1, or 2 instructions per cycle)
12 (00_1100)
Snoops serviced
Counts snoops serviced to the L1 and the L2
13 (00_1101)
Dirty L1 castouts to
L2
Incremented whenever the L1 casts out dirty data to the L2. A dirty castout is a
cache block whose D bit is 1.
14 (00_1110)
SRU instructions
completed
Counts completed instructions executed by the system register unit (SRU)
15 (00_1111)
dL1 load misses
Counts speculative load attempts that miss in the L1 data cache and were
queued either in the data reload table or load-fold queue. Does not include MMU.
16 (01_0000)
dL1 store misses
Counts write-back store attempts that missed in the L1 data cache and queued
up a new entry in the data reload table or store-miss-merged to a current data
reload table entry
17 (01_0001)
dL1 misses
Counts L1 data cache load, store, and touch misses
18 (01_0010)
L2 tag writes
Counts whenever an L2 tag needed to be written to a new state. Does not include
writes due to snoop state updates.
Table 11-8. PMC1 EventsMMCR0[19D25] Select Encodings (Continued)
Number
Event
Description