viii
MPC7400 RISC Microprocessor Users Manual
CONTENTS
Paragraph
Number
Title
Page
Number
2.3.4.3.10
2.3.4.4
2.3.4.4.1
2.3.4.4.2
2.3.4.4.3
2.3.4.4.4
2.3.4.5
2.3.4.6
2.3.4.6.1
2.3.4.6.2
2.3.4.7
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.3.1
2.3.5.4
2.3.6
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.3.1
2.3.6.3.2
2.3.6.3.3
2.3.7
2.4
2.5
2.5.1
2.5.1.1
2.5.1.2
2.5.1.3
2.5.1.4
2.5.2
2.5.2.1
2.5.2.2
2.5.2.3
2.5.2.4
2.5.2.5
2.5.3
2.5.3.1
2.5.3.2
2.5.3.3
2.5.4
Floating-Point Store Instructions.......................................................... 2-55
Branch and Flow Control Instructions...................................................... 2-57
Branch Instruction Address Calculation............................................... 2-57
Branch Instructions............................................................................... 2-58
Condition Register Logical Instructions............................................... 2-58
Trap Instructions................................................................................... 2-58
System Linkage InstructionUISA......................................................... 2-59
Processor Control InstructionsUISA .................................................... 2-59
Move to/from Condition Register Instructions..................................... 2-59
Move to/from Special-Purpose Register Instructions (UISA).............. 2-60
Memory Synchronization InstructionsUISA........................................ 2-62
PowerPC VEA Instructions.......................................................................... 2-63
Processor Control InstructionsVEA ..................................................... 2-64
Memory Synchronization InstructionsVEA......................................... 2-64
Memory Control InstructionsVEA....................................................... 2-65
User-Level Cache InstructionsVEA................................................. 2-65
Optional External Control Instructions..................................................... 2-68
PowerPC OEA Instructions.......................................................................... 2-69
System Linkage InstructionsOEA ........................................................ 2-69
Processor Control InstructionsOEA ..................................................... 2-69
Memory Control InstructionsOEA....................................................... 2-70
Supervisor-Level Cache Management Instruction(OEA) ................ 2-70
Segment Register Manipulation Instructions (OEA)............................ 2-70
Translation Lookaside Buffer Management InstructionsOEA......... 2-71
Recommended Simplified Mnemonics......................................................... 2-71
AltiVec Instructions.......................................................................................... 2-72
AltiVec UISA Instructions................................................................................ 2-73
Vector Integer Instructions ........................................................................... 2-73
Vector Integer Arithmetic Instructions..................................................... 2-73
Vector Integer Compare Instructions........................................................ 2-75
Vector Integer Logical Instructions.......................................................... 2-76
Vector Integer Rotate and Shift Instructions............................................ 2-76
Vector Floating-Point Instructions................................................................ 2-76
Vector Floating-Point Arithmetic Instructions......................................... 2-77
Vector Floating-Point Multiply-Add Instructions.................................... 2-77
Vector Floating-Point Rounding and Conversion Instructions ................ 2-78
Vector Floating-Point Compare Instructions............................................ 2-78
Vector Floating-Point Estimate Instructions ............................................ 2-79
Vector Load and Store Instructions.............................................................. 2-79
Vector Load Instructions .......................................................................... 2-79
Vector Load Instructions Supporting Alignment ..................................... 2-80
Vector Store Instructions.......................................................................... 2-80
Control Flow................................................................................................. 2-80