INDEX
Index
Index-3
C
Cache
60x bus mode
coherency protocol,
3-11
MESI protocol,
3-15
AltiVec technology
LRU instruction support,
3-51
overview,
7-15
transient hint support,
3-11
atomic memory references,
3-35
bus interface unit,
3-3
,
3-72
bus transactions,
3-72
cache arbitration,
6-12
cache block, definition,
3-5
cache coherency,
3-7
cache control
bus operations,
3-73
dcbi,
2-70
dcbt,
2-66
instructions,
3-36
,
3-40
overview,
3-36
cache hit,
6-12
cache management instructions,
2-85
,
7-6
,
A-35
cache miss,
6-15
cache miss allocation,
3-45
cache operations
data cache block fill,
3-45
data cache block push,
3-48
instruction cache block fill,
3-45
load/store operations, processor initiated,
3-33
operations,
3-45
cache/memory subsystem/BIU integration,
3-3
cache-inhibited accesses (I bit),
3-7
coherency protocols,
3-11
coherency support,
3-9
data cache
allowed cache states,
3-10
block fill operations,
3-45
block push operation,
3-48
cache block replacement selection,
3-48
configuration,
3-5
dcba instruction,
3-43
dcbf instruction,
3-43
dcbi instruction,
3-43
dcbst instruction,
3-42
dcbt instruction,
3-40
dcbtst instruction,
3-41
dcbz instruction,
3-42
enabling/disabling with HID0,
3-36
flash invalidation,
3-37
hardware flush parameter in MSSCR0,
3-39
locking using HID0,
3-36
operation,
9-4
organization,
3-5
snooping,
3-76
status bits,
3-9
store hit,
3-47
enforcing store ordering,
3-34
guarded memory bit (G bit),
3-7
instruction cache
block fill operations,
3-45
cache block replacement selection,
3-48
configuration,
3-6
enabling/disabling with HID0,
3-38
flash invalidation,
3-38
icbi instruction,
3-44
locking using HID0,
3-38
organization,
3-6
instruction cache throttling,
10-11
intervention,
3-13
L1 cache
features list,
3-1
flushing,
3-52
invalidation,
3-52
operation,
9-4
L2 cache
cache miss allocation,
3-64
cache size,
3-56
clock and timing controls,
3-60
clock configuration,
3-65
configuration,
3-54
considerations,
6-19
enabling/disabling,
3-55
flushing,
3-58
generation,
3-56
global invalidation,
3-57
hardware flush,
3-58
initialization,
3-61
interface signals,
8-39
locking using L2DO and L2IO,
3-57
operation,
3-62
organization,
3-54
overview,
3-53
parity checking,
3-56
power management,
3-61
replacement selection,
3-64
software flush,
3-59
SRAM timing examples,
3-67
SRAM types,
3-56
status bits,
3-54
store hit,
3-65
system interface operation,
9-6
test controls,
3-61
testing,
3-65
write-back/write-through modes,
3-56
load miss folding,
3-46
load/store operations, processor initiated,
3-33
memory access and sequential consistency,
3-34
memory coherency,
6-35