
5-38
MPC7400 RISC Microprocessor Users Manual
Memory Segment Model
/* Code for Modifying a Page Table Entry */
/* First delete the current page table entry */
PTE
V
<- 0
/* (other fields dont matter) */
sync
/* ensure update completed */
tlbie(old_EA)/* invalidate old translation */
eieio
/* order tlbie before tlbsync */
tlbsync /* ensure tlbie completed on all processors */
sync
/* ensure tlbsync completed */
/* Then add new PTE over old */
PTE
RPN,R,C,WIMG,PP
<- new values
eieio
/* order 1st PTE update before 2nd */
PTE
VSID,API,H,V
<- new values (V=1)
sync
/* ensure updates completed */
Processors may write referenced and changed bits with unsynchronized, atomic byte store
operations. Note that the V, R, and C bits each reside in a distinct byte of a PTE. Therefore,
extreme care must be taken to use byte writes when updating only one of these bits.
Explicitly altering certain MSR bits (using the
mtmsr
instruction), or explicitly altering
PTEs, or certain system registers, may have the side effect of changing the effective or
physical addresses from which the current instruction stream is being fetched. This kind of
side effect is deTned as an implicit branch. Implicit branches are not supported and an
attempt to perform one causes boundedly-undeTned results. Therefore, PTEs must not be
changed in a manner that causes an implicit branch. Chapter 2, òPowerPC Register Set,ó in
The
Programming Environments Manual
, lists the possible implicit branch conditions that
can occur when system registers and MSR bits are changed.
5.4.7 Segment Register Updates
Synchronization requirements for using the move to segment register instructions are
described in òSynchronization Requirements for Special Registers and for Lookaside
Buffersó in Chapter 2, òPowerPC Register Set,ó in
The
Programming Environments
Manual
.