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MPC7400 RISC Microprocessor Users Manual
AltiVec and the Memory Management Model
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A DSI exception occurs only if an AltiVec load or store operation encounters a
protection violation or a page fault (does not Tnd a valid PTE during a table search
operation). Also a DSI exception occurs if an AltiVec load or store attempts to access
a T = 1 (direct-store) memory location.
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An AltiVec assist exception may occur if an AltiVec oating-point instruction
detects denormalization data as an input or output in Java mode.
7.4 AltiVec and the Memory Management Model
The AltiVec functionality in the MPC7400 affects the MMU model in the following ways:
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A data stream instruction (
dst
(
t
) or
dstst
(
t
)) can cause table search operations to
occur after the instruction is retired.
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MMU exception conditions can cause a data stream operation to abort.
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Aborted VTQ-initiated table search operations can cause a line fetch skip.
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Execution of a
tlbsync
instruction can cancel an outstanding table search operation
for a VTQ.
Data stream touch instructions may use either of the two translation mechanisms
MSR[DR] = 1 as speciTed by the PowerPC architecturesegment/page, or BAT. For more
information, see Chapter 5, òMemory Management.ó
7.5 AltiVec Technology and Instruction Timing
The AltiVec technology deTnes additional data streaming instructions to help improve
throughput. Those instructions are described in Section 7.1.2.3, òData Stream Touch
Instructions,ó
7.5.1 Integer Store Gathering
The MPC7400 performs store gathering for write-through operations to nonguarded space.
It performs cache-inhibited stores to nonguarded space for 4-byte, word-aligned stores.
These stores are combined in the LSU to form a double word sent out on the 60x bus as a
single-beat operation. However, stores are gathered only if the successive stores meet the
criteria and are queued and pending. Store gathering occurs regardless of the address order
of the stores. Store gathering is enabled by setting HID0[SGE]. Stores can be gathered in
big-endian modes.
Store gathering is
not
done for the following:
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Stores to guarded cache-inhibited or write-through space
Byte-reverse store operations
stwcx.
instructions