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Chapter 3. L1 and L2 Cache Operation
3-43
Cache Control
The function of this instruction is independent of the WIMG bit settings of the block or PTE
containing the effective address. However, if the address is marked memory-coherency-
required, the execution of
dcbst
causes an address broadcast on the system bus. Execution
of a
dcbst
instruction does not affect the data cache or L2 cache if they are disabled.
A BAT or TLB protection violation generates a DSI exception.
3.5.3.5 Data Cache Block Flush (dcbf)
The effective address is computed, translated, and checked for protection violations as
deTned in the PowerPC architecture. This instruction is treated as a load with respect to
address translation and memory protection.
If the address hits in the cache, and the block is in the modiTed state, the modiTed block is
written back to memory and the cache block is invalidated. If the address hits in the cache,
and the cache block is in the exclusive or shared state, the cache block is invalidated. If the
address misses in the cache, no action is taken.
The function of this instruction is independent of the WIMG bit settings of the block or PTE
containing the effective address. However, if the address is marked memory-coherency-
required, the execution of
dcbf
broadcasts an address-only FLUSH transaction on the
system bus. Execution of a
dcbf
instruction does not affect data cache or L2 cache if they
are disabled.
A BAT or TLB protection violation generates a DSI exception.
3.5.3.6 Data Cache Block Allocate (dcba)
The MPC7400 implements the data cache block allocate (
dcba
) instruction. This is
currently an optional instruction in the PowerPC virtual environment architecture (VEA);
however, it may become required in future versions of the architecture. The
dcba
instruction provides potential system performance improvement through the use of a
software-initiated pre-store hit. This allows software to establish a block in the data cache
in anticipation of a store into that block, without loading the block from memory.
The MPC7400 executes the
dcba
instruction the same as a
dcbz
instruction, with one major
exception. In cases when
dcbz
causes an exception, a
dcba
will no-op. Note that this means
that a
dcba
/DABR address match does not cause an exception.
3.5.3.7 Data Cache Block Invalidate (dcbi)
The effective address is computed, translated, and checked for protection violations as
deTned in the PowerPC architecture. This instruction is treated as a store with respect to
address translation and memory protection.
If the address hits in the cache, the cache block is invalidated, regardless of the state of the
cache block. Because this instruction may effectively destroy modiTed data, it is privileged
(that is,
dcbi
is available to programs at the supervisor privilege level, MSR[PR] = 0).