
INDEX
Index
Index-1
A
AACK (address acknowledge) signal,
8-15
,
8-32
ABB (address bus busy) signal,
8-9
,
9-10
Abbreviations and acronyms,
xlii
About this book,
xxxv
Acronyms and abbreviations,
xlii
Address bus
60x bus mode
address arbitration,
9-11
address bus streaming,
9-42
address tenure,
9-9
address transfer attribute signals,
8-12
,
9-16
address transfer signals,
8-9
,
9-15
address transfer start signals,
8-11
address transfer termination,
8-15
,
9-21
address transfer timing diagrams,
9-15
arbitration signals,
8-8
,
9-10
bus parking,
9-13
split-bus transactions,
9-11
MPX bus mode
address bus streaming,
9-42
address transfer attribute signals,
8-29
address transfer signals,
8-28
,
9-41
address transfer start signals,
8-29
address transfer termination,
8-32
arbitration signals,
8-26
Address translation,
see
Memory management unit
Addressing modes,
2-39
Alignment
data transfers,
9-19
,
9-21
,
9-44
exception,
4-21
misaligned accesses,
2-34
rules,
2-34
AltiVec technology
cache
LRU instruction support,
3-51
overview,
7-15
transient hint support (data),
3-11
exceptions
AltiVec assist exception,
4-1
,
4-26
AltiVec unavailable exception,
4-1
,
4-28
DSI exception,
4-1
,
4-20
overview,
7-15
instruction timing
data stream termination,
7-8
data stream touch instructions and sync,
7-8
data stream touch instructions and tlbsync,
7-8
dss and dssall instructions,
7-10
dst vs. dstt instructions (differences),
7-10
dstst vs. dststt instructions (differences),
7-10
execution latency,
6-46
implementation-specific features,
7-1
LRU instructions,
7-5
overview,
6-1
,
7-1
,
7-16
pipeline stalls (data stream instructions),
7-7
speculative
execution
instructions),
7-7
static data stream touch instructions,
7-8
stream engine tags,
7-7
transient data stream touch instructions,
7-8
VALU execution timing,
6-33
VCIU execution timing,
6-33
vector float behavior,
7-11
vector FP compare, min, max in Java mode,
7-13
vector FP compare, min, max in non-Java
mode,
7-12
VFPU execution timing,
6-33
VPU execution timing,
6-33
VSIU execution timing,
6-33
instructions
denormalization,
7-12
implementation-specific LRU instruction,
7-11
instruction set,
1-32
,
2-72
,
6-33
,
7-4
round-to-integer in Java mode,
7-14
round-to-integer in non-Java mode,
7-14
integer store gathering,
7-16
memory management unit,
5-1
,
7-16
performance monitor,
11-1
programming model,
7-1
reference books,
xxxvii
register file structure,
7-2
registers,
1-28
transient instructions,
7-5
vector arithmetic logic unit (VALU),
1-13
vector permute unit (VPU),
1-12
AMON (address bus monitor) signal,
8-27
A
n
(address bus) signals,
8-9
,
8-28
APE (address parity error) signal,
9-16
AP
n
(address parity) signals,
8-10
,
8-28
Arbitration, system bus,
9-24
Arithmetic instructions
floating-point,
A-27
integer,
2-72
,
A-25
vector floating-point,
2-77
vector integer,
2-73
ARTRY (address retry) signal,
8-15
,
8-32
(data
stream