Chapter 3. L1 and L2 Cache Operation
3-55
L2 Cache Interface
The L2 cache tag also contains a FIFO replacement bit (F-bit) for each index. The F-bit is
used for selecting a replacement target upon L2 cache reload. It is updated when a new tag
is allocated in the L2 cache tag.
3.7.3 L2 Cache Control Register (L2CR)
The L2 cache control register (L2CR) allows control of L2 cache conTguration, timing, and
operation. The following sections describe the L2 cache control parameters in the L2CR.
The L2CR is a supervisor-level read/write, implementation-speciTc register that is accessed
as SPR 1017. The contents of the L2CR are cleared during power-on reset. See
Section 2.1.7, òL2 Cache Control Register (L2CR),ó for additional information about the
conTguration of the L2CR.
3.7.3.1 Enabling and Disabling the L2 Cache
The L2 cache may be enabled or disabled by programming the L2CR[L2E] parameter. This
parameter enables or disables the operation of the L2 cache (including snooping) starting
with the next transaction that the L2 cache unit receives. When the L2 cache is disabled, the
cache tag status bits are ignored and all accesses are propagated to the system bus. Note that
if the L2 cache is enabled, the L1 data cache must also be enabled. Conversely, if the L1
data cache is disabled, the L2 cache must also be disabled.
Before enabling the L2 cache, the L2 clock must Trst be conTgured through the
L2CR[L2CLK] bits, and a period of time must elapse for the L2 DLL to stabilize. See the
MPC7400 hardware speciTcations for the DLL stabilization interval. Also before enabling
the L2 cache, all other bits in the L2CR must be set appropriately, and the L2 cache may
need to be globally invalidated. See Section 3.7.4, òL2 Cache Initialization,ó for a
description of the L2 cache initialization procedures.
Before the L2 cache is disabled it must be ushed to prevent coherency problems. The
cache management instructions
dcbf
,
dcbst
, and
dcbi
do not affect the L1 data cache or L2
cache when they are disabled.
Table 3-11. Legal L2 Cache States
MSV value
MERSI state
Comments
M
S
V
1
0
1
ModiTed
cast out from data cache
0
0
1
Exclusive
could be instruction or data
1
1
1
Recent
could be instruction or data
0
1
1
Shared
could be instruction or data
x
x
0
Invalid
invalid line