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MPC7400 RISC Microprocessor Users Manual
MPC7400 Microprocessor: Implementation
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Cache implementationSection 1.6, òOn-Chip Cache Implementation,ó describes
the cache model that is deTned generally for PowerPC processors by the virtual
environment architecture. It also provides speciTc details about the MPC7400 cache
implementation. The information in this section is described more fully in
Chapter 3, òL1 and L2 Cache Operation.ó
Exception modelSection 1.7, òException Model,ó describes the exception model
of the PowerPC operating environment architecture and the differences in the
MPC7400 exception model. The information in this section is described more fully
in Chapter 4, òExceptions.ó
Memory managementSection 1.8, òMemory Management,ó describes generally
the conventions for memory management among the PowerPC processors. This
section also describes the MPC7400s implementation of the 32-bit PowerPC
memory management speciTcation. The information in this section is described
more fully in Chapter 5, òMemory Management.ó
Instruction timingSection 1.9, òInstruction Timing,ó provides a general
description of the instruction timing provided by the superscalar, parallel execution
supported by the PowerPC architecture and the MPC7400. The information in this
section is described more fully in Chapter 6, òInstruction Timing.ó
Power managementSection 1.10, òPower Management,ó describes how the power
management can be used to reduce power consumption when the processor, or
portions of it, are idle. The information in this section is described more fully in
Chapter 10, òPower and Thermal Management.ó
Thermal managementSection 1.11, òThermal Management,ó describes how the
thermal management unit and its associated registers (THRM1DTHRM3) and
exception can be used to manage system activity in a way that prevents exceeding
system and junction temperature thresholds. This is particularly useful in
high-performance portable systems, which cannot use the same cooling mechanisms
(such as fans) that control overheating in desktop systems. The information in this
section is described more fully in Chapter 10, òPower and Thermal Management.ó
Performance monitorSection 1.12, òPerformance Monitor,ó describes the
performance monitor facility, which system designers can use to help bring up,
debug, and optimize software performance. The information in this section is
described extensively in Chapter 11, òPerformance Monitor.ó
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The following sections summarize the features of the MPC7400, distinguishing those that
are deTned by the architecture from those that are unique to the MPC7400 implementation.
The PowerPC architecture consists of the following layers, and adherence to the PowerPC
architecture can be described in terms of which of the following levels of the architecture
is implemented: