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MPC7400 RISC Microprocessor Users Manual
MPX Bus Signal ConTguration
State Meaning
Asserted/NegatedRepresent the state of data during a data write
transaction or a data-only (data intervention) transaction. Byte lanes
not selected for data transfer do not supply valid data.
Timing Comments
Assertion/NegationInitial beat occurs one bus clock cycle after a
qualiTed DBG is sampled, and, for bursts, transitions on the bus in
the clock cycle following each assertion of TA.
High ImpedanceSame as 60x bus interface
8.4.7.1.2 Data Bus (DH[0:31], DL[0:31])Input
Following are the state meaning and timing comments for the DH[0:31], DL[0:31] signals
as inputs in MPX bus mode.
State Meaning
Asserted/NegatedSame as 60x bus interface, except that these
signals are also used for data-only transactions in MPX bus mode.
Timing Comments
Assertion/NegationSame as 60x bus interface
8.4.7.2 Data Bus Parity (DP[0:7])Output
Following are the state meaning and timing comments for the DP[0:7] signals as outputs in
MPX bus mode.
State Meaning
Asserted/NegatedSame as 60x bus interface, except that they are
also driven for data-only transactions in MPX bus mode.
High ImpedanceSame as 60x bus interface
Timing Comments
Assertion/NegationSame as DH[0:31], DL[0:31]
High ImpedanceSame as DH[0:31], DL[0:31]
8.4.7.3 Data Bus Parity (DP[0:7])Input
Following are the state meaning and timing comments for the DP[0:7] signals as inputs in
MPX bus mode.
State Meaning
Asserted/NegatedSame as 60x bus interface., except that these
signals are also used for data-only transactions in MPX bus mode.
Timing Comments
Assertion/NegationSame as DH[0:31], DL[0:31]
8.4.8 Data Transfer Termination Signals in MPX Bus Mode
The function of the data termination signals in MPX bus mode is similar to that in 60x bus
mode. The differences are described in the following subsections. For a detailed description
of how these signals interact in MPX bus mode, see Section 9.6.2.3, òData Termination
Phase in MPX Bus Mode.ó