Chapter 3. L1 and L2 Cache Operation
3-1
Chapter 3
L1 and L2 Cache Operation
The MPC7400 microprocessor contains separate 32-Kbyte, eight-way set associative
level 1 (L1) instruction and data caches to allow the execution units and registers rapid
access to instructions and data. In addition, the MPC7400 microprocessor features an
integrated level 2 (L2 cache) cache controller.
This chapter describes the organization of the on-chip L1 instruction and data caches, cache
coherency protocols, cache control instructions, various cache operations, the L2 cache
controller, and the interaction between the caches, the load/store unit (LSU), the instruction
unit, the memory subsystem, and the bus interface unit (BIU).
Note that in this chapter, the term multiprocessor is used in the context of maintaining
cache coherency. These multiprocessor devices could be actual processors or other devices
that can access system memory, maintain their own caches, and function as bus masters
requiring cache coherency.
AltiVec Technology and the Cache Implementation
The implementation of AltiVec technology in the MPC7400 has implications that affect the
cache model, speciTcally:
¥
AltiVec transient instructions (
dstt
,
dststt
,
lvxl
,
stvxl
), described in Section 3.4.2.1,
òAltiVec Transient Hint Supportó
¥
Store miss merging, described in Section 3.6.5, òStore Miss Mergingó
¥
AltiVec LRU instructions (
lvxl
,
stvxl
), described in Section 3.6.8.1, òAltiVec LRU
Instruction Supportó
¥
External system bus transactions caused by caching-inhibited AltiVec loads and
stores, or write-through AltiVec stores, described in Section 3.9, òMPC7400 Caches
and System Bus Transactionsó
3.1 L1 Instruction and Data Caches
The MPC7400 L1 cache implementation has the following characteristics:
¥
Two separate 32-Kbyte instruction and data caches (Harvard architecture).
¥
Both instruction and data caches are eight-way set associative.