9-44
MPC7400 RISC Microprocessor Users Manual
MPX Bus Protocol
9.6.1.3.3 Aligned and Misaligned Transfers
Performance on misaligned transfers may be substantially less than on aligned transfers,
and it is recommended that software attempt to align code and data if possible. See
Section 9.3.2.4, òEffect of Alignment in Data Transfers,ó for a detailed description of
alignment considerations for transactions in 60x and MPX bus modes.
9.6.1.4 Address Termination Phase in MPX Bus Mode
The address tenure is terminated by the assertion of the AACK input. In 60x bus mode, the
60x interface forces a turn-around cycle on the bus between each address tenure (because
the system must provide AACK no earlier than the cycle following the assertions of TS)
implying that 60x address tenures last at least three bus clock cycles.
Because MPX bus mode supports address bus streaming, the MPC7400 can drive
consecutive address tenures without a dead cycle in between. Using address bus streaming,
two-cycle address tenures are possible if AACK is not delayed and the same master receives
a qualiTed bus grant to drive another address tenure. Note that to accommodate address bus
streaming, AACK must be asserted for only one bus clock cycle in MPX bus mode.
The address tenure can be terminated with the assertion of ARTRY anytime during the
address tenure and through the cycle following AACK in MPX bus mode the same as in
60x bus mode. As a snooper (if data intervention is not enabled), the MPC7400 asserts
ARTRY similarly (and for the same conditions) to the 60x bus mode. As a bus master, the
MPC7400 also responds to the assertion of ARTRY in the same way as in 60x bus mode.
See Section 3.4.3, òCoherency Protocols.ó
Negated
0
0
1
1 byte
Negated
0
1
0
2 bytes
Negated
0
1
1
3 bytes
Negated
1
0
0
4 bytes
Negated
1
0
1
5 bytes (N/A)
Negated
1
1
0
6 bytes (N/A)
Negated
1
1
1
7 bytes (N/A)
Notes:
3-byte transfers may be requested by the MPC7400 starting at
any byte address within the double word from byte address 0 to
byte address 5.
4-byte transfers may be requested by MPC7400 starting at any
byte address within the double word from byte address 0 to
byte address 4.
Table 9-7. TBST and TSIZ[0:2] Encodings in MPX Bus Mode (Continued)
TBST
TSIZ0
TSIZ1
TSIZ2
Transfer Size