10-6
MPC7400 RISC Microprocessor Users Manual
Programmable Power Modes
Due to the fully static design of the MPC7400, the internal processor state is preserved
when no internal clock is present. Because the time base and decrementer are disabled
while the MPC7400 is in sleep mode, the MPC7400s time base contents must be updated
from an external time base after exiting sleep mode if accurate time-of-day is required.
Before entering sleep mode, the MPC7400 asserts QREQ to indicate that it is ready to
disable bus snooping. When the system ensures that snooping is no longer necessary, it
asserts QACK and the MPC7400 enters sleep mode.
Note the following with respect to sleep mode:
¥
¥
All functional units are disabled (including bus snooping and time base).
All nonessential input receivers are disabled:
Internal clock regenerators are disabled.
PLL and DLL are still running (see below).
PLL and DLL may be disabled and SYSCLK may be removed while in sleep mode.
¥
10.2.4.5 Entering Sleep Mode
Sleep mode is entered by setting the sleep bit (HID0[10]) and MSR[POW]) and clearing
the doze and nap bits (HID0[8] and HID0[9]). The MPC7400 asserts QREQ and the system
asserts QACK. The MPC7400 enters sleep mode after several processor clocks.
10.2.4.6 Returning to Full-Power Mode
When the processor is recovering from sleep mode, SYSCLK must be enabled before the
PLL if it had been stopped in sleep mode. If the PLL had not been disabled after PLL
start-up and re-lock time (indicated in the hardware speciTcations) has elapsed, the system
logic should assert one of the sleep mode recovery signals, such as INT or SMI. After the
PLL is enabled, the DLL is reconTgured and the DLL relock time has elapsed (640 L2
clock cycles), the L2 cache may be reenabled through the L2CR.
10.2.5 Power Management Software Considerations
Because the MPC7400 is a dual-issue processor with out-of-order execution capability,
care must be taken in how the power management mode is entered. Furthermore, nap and
sleep modes require all outstanding bus operations to be completed before these power
management modes are entered. Normally, during system conTguration time, a power
management mode would be selected by setting the appropriate HID0 mode bit. Later on,
the power management mode is invoked by setting MSR[POW]. To ensure a clean
transition into and out of a power management mode, execute the following code sequence: