Chapter 1. Overview
1-41
Power Management
positions in the completion queue. If completion logic detects an instruction causing
an exception, all following instructions are cancelled, their execution results in
rename registers are discarded, and instructions are fetched from the appropriate
exception vector.
Because the PowerPC architecture can be applied to such a wide variety of
implementations, instruction timing varies among PowerPC processors.
For a detailed discussion of instruction timing with examples and a table of latencies for
each execution unit, see Chapter 6, òInstruction Timing.ó
1.10 Power Management
The MPC7400 provides four power modes, selectable by setting the appropriate control
bits in the MSR and HID0 registers. The four power modes are as follows:
¥
Full-powerThis is the default power state of the MPC7400. The MPC7400 is fully
powered and the internal functional units are operating at the full processor clock
speed. If the dynamic power management mode is enabled, functional units that are
idle will automatically enter a low-power state without affecting performance,
software execution, or external hardware.
DozeAll the functional units of the MPC7400 are disabled except for the time
base/decrementer registers, the thermal assist unit, and the bus snooping logic.
When the processor is in doze mode, an external asynchronous interrupt, a system
management interrupt, a decrementer exception, a hard or soft reset, or machine
check brings the MPC7400 into the full-power state. The MPC7400 in doze mode
maintains the PLL in a fully powered state and locked to the system external clock
input (SYSCLK) so a transition to the full-power state takes only a few processor
clock cycles.
NapThe nap mode further reduces power consumption by disabling bus snooping,
leaving only the decrementer/time base registers, the thermal assist unit, the PLL,
and the DLL (for L2 RAM clocks) in a powered state. The MPC7400 returns to the
full-power state upon receipt of an external asynchronous interrupt, a system
management interrupt, a decrementer exception, a hard or soft reset, or a machine
check input (MCP). A return to full-power state from a nap state takes only a few
processor clock cycles. When the processor is in nap mode, if QACK is negated, the
processor is put in doze mode to support snooping.
SleepSleep mode minimizes power consumption by disabling all internal
functional units, after which external system logic may disable the PLL and
SYSCLK. Returning the MPC7400 to the full-power state requires the enabling of
the PLL and SYSCLK, followed by the assertion of an external asynchronous
interrupt, a system management interrupt, a hard or soft reset, or a machine check
input (MCP) signal after the time required to relock the PLL.
¥
¥
¥