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2-52
MPC7400 RISC Microprocessor Users Manual
Instruction Set Summary
2.3.4.3.4 Integer Store Instructions
For integer store instructions, the contents of
r
S are stored into the byte, half word, word or
double word in memory addressed by the EA (effective address). Many store instructions
have an update form, in which
r
A is updated with the EA. For these forms, the following
rules apply:
¥
¥
If
r
A
1
0, the effective address is placed into
r
A.
If
r
S =
r
A, the contents of register
r
S are copied to the target memory element, then
the generated EA is placed into
r
A (
r
S).
The
PowerPC architecture deTnes store with update instructions with
r
A = 0 as an invalid
form. In addition, it deTnes integer store instructions with the CR update option enabled
(Rc Teld, bit 31, in the instruction encoding = 1) to be an invalid form. Table 2-31
summarizes the integer store instructions.
Table 2-31. Integer Store Instructions
2.3.4.3.5 Integer Store Gathering
The MPC7400 performs store gathering for write-through accesses to nonguarded space or
to cache-inhibited stores to nonguarded space if the stores are 4 bytes and they are
word-aligned. These stores are combined in the load/store unit (LSU) to form a double
word and are sent out on the system bus as a single-beat operation. However, stores can be
gathered only if the successive stores that meet the criteria are queued and pending. Store
Load Word and Zero with Update
lwzu
r
D
,d
(
r
A
)
Load Word and Zero with Update Indexed
lwzux
r
D
,r
A
,r
B
Name
Mnemonic
Syntax
Store Byte
stb
r
S
,d(r
A
)
Store Byte Indexed
stbx
r
S
,r
A
,r
B
Store Byte with Update
stbu
r
S
,d(r
A
)
Store Byte with Update Indexed
stbux
r
S
,r
A
,r
B
Store Half Word
sth
r
S
,d(r
A
)
Store Half Word Indexed
sthx
r
S
,r
A
,r
B
Store Half Word with Update
sthu
r
S
,d(r
A
)
Store Half Word with Update Indexed
sthux
r
S
,r
A
,r
B
Store Word
stw
r
S
,d(r
A
)
Store Word Indexed
stwx
r
S
,r
A
,r
B
Store Word with Update
stwu
r
S
,d(r
A
)
Store Word with Update Indexed
stwux
r
S
,r
A
,r
B
Table 2-30. Integer Load Instructions (Continued)
Name
Mnemonic
Syntax