Chapter 9. System Interface Operation
9-19
60x Address Bus Tenure
9.3.2.2.3 Write-Through (WT), Cache Inhibit (CI), and Global (GBL) Signals
In general, the MPC7400 provides the WT, CI, and GBL signals to indicate the status of a
transaction target as determined by the WIM bit settings during address translation by the
MMU. There are exceptions, as described in Section 3.9.2, òTransfer Attributes.ó
9.3.2.3 Burst Ordering During Data Transfers
During burst data transfer operations, 32 bytes of data (one cache line) are transferred to or
from the cache in order. However, since burst reads are performed critical double word Trst,
a burst read transfer may not start with the Trst double word of the cache line, and the cache
line Tll may wrap around the end of the cache line. Non-intervention burst write transfers
(the only burst writes performed in 60x bus mode) are always performed zero double word
Trst. Intervention burst writes (see Section 9.6.2, òData Tenure in MPX Bus Mode,ó) are
performed critical double word Trst.
The MPC7400 allows the transfer of any block of contiguous bytes within a double word.
No single bus transactions may cross a double-word boundary. Transfers of strings of data
that are aligned in such a way that they cross a double-word boundary must be broken down
into multiple bus transactions.
Table 9-3 describes the order of the double words (DW) transferred during burst operations.
Table 9-3. Burst Ordering
9.3.2.4 Effect of Alignment in Data Transfers
Table 9-4
lists the aligned transfers that can occur on the MPC7400 bus. These are transfers
in which the data is aligned to an address that is an integral multiple of the size of the data.
For example, Table 9-4 shows that 1-byte data is always aligned; however, for a 4-byte
word to be aligned, it must be oriented on an address that is a multiple of 4.
Data Transfer
For Starting Address:
A[27:28] = 00
A[27:28] = 01
A[27:28] = 10
A[27:28] = 11
First data beat
DW0
DW1
DW2
DW3
Second data beat
DW1
DW2
DW3
DW0
Third data beat
DW2
DW3
DW0
DW1
Fourth data beat
DW3
DW0
DW1
DW2
Note:
A[29:31] are always 0b000 for burst transfers performed by the MPC7400.