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MPC7400 RISC Microprocessor Users Manual
Timing Considerations
6.3.2 Instruction Fetch Timing
Instruction fetch latency depends on whether the fetch hits the BTIC, the on-chip
instruction cache, or the L2 cache, if one is implemented. If no cache hit occurs, a memory
transaction is required in which case fetch latency is affected by bus trafTc, bus clock speed,
and memory translation. These issues are discussed further in the following sections.
6.3.2.1 Cache Arbitration
When the instruction fetcher requests instructions from the instruction cache, two things
may happen. If the instruction cache is idle and the requested instructions are present, they
are provided on the next clock cycle. However, if the instruction cache is busy due to a
cache-line-reload operation, instructions cannot be fetched until that operation completes.
6.3.2.2 Cache Hit
If the instruction fetch hits the instruction cache, it takes only one clock cycle after the
request for as many as four instructions to enter the instruction queue. Note that the cache
is not blocked to internal accesses during a cache reload completes (hits under misses). The
critical double word is written simultaneously to the cache and forwarded to the requesting
unit, minimizing stalls due to load delays.
Figure 6-5 shows a simple example of instruction fetching that hits in the on-chip cache.
This example uses a series of integer add and double-precision oating-point add
instructions to show how the number of instructions to be fetched is determined, how
program order is maintained by the IQ and CQ, how instructions are dispatched and retired
in pairs (maximum), and how the FPU, IU1, and IU2 pipelines function. The following
instruction sequence is examined:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
add
fadd
add
fadd
br 6
fsub
fadd
fadd
add
add
add
add
fadd
add
fadd
.
.
.