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MPC7400 RISC Microprocessor Users Manual
MPC7400 Microprocessor Features
Supports pipelined (register-register) synchronous burst SRAMs, PB3 pipelined
(register-register) synchronous burst SRAMs, and pipelined (register-register)
late-write synchronous burst SRAMs
Core-to-L2 frequency divisors of
1,
1.5,
2,
2.5,
3,
3.5, and
4 supported
64-bit data bus
Separate memory management units (MMUs) for instructions and data
52-bit virtual address; 32-bit physical address
Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte
segments
Memory programmable as write-back/write-through, cacheable/noncacheable,
and coherency enforced/coherency not enforced on a page or block basis
Separate IBATs and DBATs (four each) also deTned as SPRs
Separate instruction and data translation lookaside buffers (TLBs)
D Both TLBs are 128-entry, two-way set associative, and use LRU replacement
algorithm
D TLBs are hardware-reloadable (that is, the page table search is performed in
hardware)
EfTcient data ow
All data buses between VRs, LSU, L1 and L2 caches, and the bus are 128 bits
wide
The L1 data cache is fully pipelined to provide 128 bits/cycle to/from the VRs
The L2 cache is fully pipelined to provide 64 bits per L2 clock cycle to the L1
caches
Up to 8 outstanding, out-of-order, cache misses allowed between the L1 data
cache and L2/bus
Up to seven out-of-order transactions on the bus, one in progress and six pending
Load folding to fold new L1 data cache misses into older, outstanding load and
store misses to the same line
Store miss merging for multiple store misses to the same line. Only coherency
action taken (address-only) for store misses merged to all 32 bytes of a cache
block (no data tenure needed).
Two-entry Tnished store queue and 4-entry completed store queue between the
LSU and the L1 data cache
Separate additional queues for efTcient buffering of outbound data (such as cast
outs and write throughs) from the L1 data cache and L2
Multiprocessing support features include the following:
Hardware-enforced, cache coherency protocols for data cache
D 3-state (MEI) similar to the MPC750
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