
10-2
MPC7400 RISC Microprocessor Users Manual
Programmable Power Modes
Software selects these modes by setting one (and only one) of the three power saving mode
bits in HID0. Hardware can enable a power management state through external
asynchronous interrupts. Such a hardware interrupt transfers the program ow to the
system management interrupt (SMI) exception handler, which then sets the appropriate
power-saving mode. A decrementer interrupt can be used to return to full power from nap
or doze mode after a predetermined duration.
Figure 10-1 shows the MPC7400 power management state diagram. Because bus snooping
is disabled in sleep mode, a hardware handshake is provided to ensure coherency before the
MPC7400 enters this power management mode.
Figure 10-1. Power Management State Diagram
Doze
Bus snooping
Data cache as needed
Decrementer timer
Software
External asynchronous exceptions
Decrementer interrupt
Performance monitor interrupt
Thermal management interrupt
Reset
Nap
Snooping enabled by negating
QACK
Decrementer timer
Hardware and software External asynchronous exceptions
Decrementer interrupt
Performance monitor interrupt
Thermal management interrupt
Reset
Sleep
None
Hardware and software External asynchronous exceptions
Performance monitor interrupt
Thermal management interrupt
Reset
Table 10-1. Programmable Power Modes (Continued)
Mode
Functioning Units
Activation Method
Full-Power Wake-Up Method
Full On
HID0[DOZE] = 1 & MSR[POW]
£
1
INT, SMI, HRESET, SRESET, DEC,
PFM, TMI, machine check interrupts
HID0[NAP] = 1 &
MSR[POW]
£
1
INT, SMI, HRESET, SRESET,
DEC, PFM, TMI, MCP
Nap
QACK asserted
and bus unit idle
QACK negated
for at least 4 clocks
Doze
HID0[SLEEP] = 1 & MSR[POW]
£
1
INT, SMI, HRESET, SRESET,
PFM, TMI, MCP
Sleep