Index-10
MPC106 PCIB/MC User's Manual
MOTOROLA
INDEX
write operations,
6-67
ROM interface
16-Mbyte ROM system,
6-61
burst read timing,
6-65
interface timing,
6-63
ROM address signals,
2-27
see also
Memory interface
RTC signal,
2-31
,
6-29
,
A-5
S
SDBA0 (SDRAM internal bank select) signal,
2-32
SDCAS (SDRAM column address strobe) signal,
2-32
SDMA
n
(SDRAM address) signals,
2-32
SDRAM interface operation
128-Mbyte SDRAM system,
6-41
bank-activate command,
6-46
burst operations,
6-43
command encodings,
6-47
configurations supported,
6-42
JEDEC interface commands,
6-46
mode-set command,
6-47
,
6-55
overview,
6-40
power saving modes,
6-58
power-on initialization,
6-45
precharge-all-banks command,
6-46
precharge-bank command,
6-46
programmable parameters,
6-45
read-with-autoprecharge command,
6-46
refresh
command,
6-47
description,
6-56
self-refresh command,
6-47
timing diagrams
burst-of-four read timing,
6-50
burst-of-four write timing,
6-51
self-refresh entry timing,
6-59
self-refresh exit timing,
6-60
single-beat read timing,
6-53
single-beat write timing,
6-54
write-with-autoprecharge command,
6-47
SDRAM power-on initialization,
6-45
SDRAS (SDRAM row address strobe) signal,
2-32
Secondary (L2) cache
,
see
L2 interface
Self-refresh command, SDRAM,
6-47
SERR (system error) signal,
2-38
,
7-26
,
9-5
Signal buffering
flow-through buffers,
6-3
memory interface buffer configurations,
6-2
parity/ECC path read control,
6-6
registered buffers,
6-4
transparent latch buffers,
6-4
Signals
60x address/data bus arbitration,
4-7
AACK,
2-9
,
4-16
AD
n
,
2-33
,
7-6
ADS,
2-20
,
5-39
alternate functions, list,
2-3
A
n
,
2-9
AR
n
,
2-27
,
6-62
ARTRY,
2-10
,
4-17
BA0,
2-20
BAA,
2-20
BCTL
n
,
2-27
,
6-2
BGL2,
2-24
,
5-43
BG
n
,
2-11
,
2-25
,
4-7
BRL2,
2-24
,
5-43
BR
n
,
2-11
,
2-26
,
4-7
C/BE
n
,
2-33
,
7-8
,
7-25
CAS
n
,
2-28
,
6-9
,
6-29
CI,
2-12
CK0,
2-40
CKE,
2-28
configuration signals,
2-43
CS
n
,
2-28
DBGL2,
2-24
,
5-43
DBGLB,
2-12
,
4-21
DBG
n
,
2-12
,
2-26
,
3-1
,
4-7
DCS,
2-21
,
5-3
–
5-6
DEVSEL,
2-35
,
7-7
DH
n
/DL
n
,
2-13
,
6-7
DIRTY_IN,
2-21
,
5-10
DIRTY_OUT,
2-22
,
5-10
DOE,
2-22
,
3-62
,
5-26
DQM
n
,
2-29
DWE
n
,
2-22
,
5-3
error signals,
2-40
,
9-3
FLSHREQ,
2-39
,
7-27
FNR,
2-44
FOE,
2-29
,
6-67
FRAME,
2-35
,
7-3
GBL,
2-14
GNT,
2-35
,
7-3
HIT,
2-22
,
2-25
,
5-10
HRST,
2-40
,
9-3
,
A-2
IEEE 1149.1 interface,
2-42
,
C-2
interrupt and error signals,
2-40
,
9-3
interrupt signal connections, examples,
9-10
interrupt signals,
2-40
,
9-3
interrupt, clock, and power management,
2-40
IRDY,
2-36
,
7-3
ISA_MASTER,
2-39
,
7-26
JTAG signals,
2-42
,
C-2
L2 cache interface signals,
2-19
LBCLAIM,
2-14
,
4-21
LOCK,
2-36
,
7-23
MA
n
,
2-29
,
6-10
MCP,
2-14
,
4-19
,
9-3
MDLE,
2-29
,
6-4