
MOTOROLA
Chapter 6. Memory Interface
6-9
be configured to provide 13, 12, 11, 10, or 9 row address bits to a particular bank, and 12,
11, 10, or 9 column address bits. Note that for devices with 13 row address bits, only 11
column address bits can be provided for a 1-Gbyte address space.
The data path to the memory banks must be 64 bits wide (72 with parity or ECC). When
ECC or read-modify-write parity is enabled, all memory accesses are performed a double
word at a time (that is, all CAS signals are asserted simultaneously). However, when ECC
or read-modify-write parity is disabled, the memory system design must use the CAS
signals for byte lane selection. Table 6-2 summarizes some of the memory configurations
supported by the MPC106.
By using a memory polling algorithm at power-on reset, system firmware configures the
MPC106 to correctly map the size of each bank in memory (using the memory boundary
registers). The MPC106 uses its bank map to assert the appropriate RAS signal for memory
accesses according to the provided bank depths.
6.3.2 DRAM/EDO Address Multiplexing
System software must configure the MPC106 at power-on reset to appropriately multiplex
the row and column address bits for each bank. This is done by writing the row address
configuration into a specific configuration register. Address multiplexing will then occur
according to the configuration settings, as shown in Figure 6-5.
Table 6-2. Supported Memory Device Configurations
Number of
Devices in a
Bank
Device
Configuration
Row Bits x
Column Bits
Bank Size
Maximum
Memory
(Using All 8
Banks)
16
16M x 4
13 x 11
128 Mbytes
1 Gbyte
64
16M x 1
12 x 12
128 Mbytes
1 Gbyte
16
4M x 4
12 x 10
32 Mbytes
256 Mbytes
16
4M x 4
11 x 11
32 Mbytes
256 Mbytes
64
4M x 1
11 x 11
32 Mbytes
256 Mbytes
8
2M x 8
11 x 10
16 Mbytes
128 Mbytes
4
1M x 16
10 x 10
8 Mbytes
64 Mbytes
16
1M x 4
10 x 10
8 Mbytes
64 Mbytes
64
1M x 1
10 x 10
8 Mbytes
64 Mbytes
8
512K x 8
10 x 9
4 Mbytes
32 Mbytes
4
256K x 16
9 x 9
2 Mbytes
16 Mbytes
16
256K x 4
9 x 9
2 Mbytes
16 Mbytes