MOTOROLA
About This Book
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About This Book
The primary objective of this user’s manual is to describe the functionality of the MPC106
PCI bridge/memory controller (PCIB/MC) for use by systems designers and software
developers. The MPC106 is one device in a family of products that provides system-level
support for industry-standard interfaces to be used with PowerPC microprocessors.
In this document, the term ‘60x’ is used to denote a 32-bit microprocessor from the
PowerPC architecture family that conforms to the bus interface of the PowerPC 601,
PowerPC 603, or PowerPC 604 microprocessors. Note that this does not include the
PowerPC 602 microprocessor which has a multiplexed address/data bus. 60x processors
implement the PowerPC architecture as it is specified for 32-bit addressing, which provides
32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and
floating-point data types of 32 and 64 bits (single-precision and double-precision).
It must be kept in mind that each PowerPC processor is a unique PowerPC implementation.
It is beyond the scope of the manual to provide a thorough description of the PowerPC
architecture; refer to
PowerPC Microprocessor Family: The Programming Environments
for more information about the architecture. It is also beyond the scope of the manual to
provide a thorough description of the PCI local bus; refer to
and
PCI System Design Guide
for more information about the PCI bus.
PCI Local Bus Specification
To locate any published errata or updates for this document, refer to the website at
http://www.mot.com/powerpc/.
Audience
This manual is intended for system software and hardware developers who want to develop
products incorporating PowerPC microprocessors and the PCI bus. It is assumed that the
reader understands operating systems, microprocessor system design, and the basic
principles of reduced instruction set computing (RISC) processing.