Index-8
MPC106 PCIB/MC User's Manual
MOTOROLA
INDEX
features list,
1-3
I/O space addressing,
7-7
linear incrementing,
7-6
little-endian mode transfers to I/O space,
B-12
little-endian mode transfers to memory space,
B-9
master-abort transaction termination,
7-11
,
9-9
memory space addressing,
7-6
MPC106 as PCI bus master,
7-2
MPC106 as PCI target,
7-2
nonmaskable interrupt,
2-41
,
9-10
overview,
1-6
,
7-1
PCI command encodings,
7-4
PCI commands
interrupt-acknowledge transaction,
7-21
special-cycle command,
7-22
PCI Local Bus Specification
,
xxvii
,
3-22
PCI special-cycle operations,
7-23
,
A-7
PCI System Design Guide
,
xxvii
,
3-22
PCI-to-ISA bridge,
7-27
,
9-5
PCI-to-system memory read buffer (PCMRB),
8-5
PCI-to-system
memory
(PCMWBs),
8-5
processor-to-PCI read buffer (PRPRB),
8-4
processor-to-PCI-write buffers (PRPWBs),
8-5
registers
bus error status register,
3-35
,
9-9
CONFIG_ADDR register,
3-8
,
3-15
,
7-17
CONFIG_DATA register,
3-8
,
3-15
,
7-18
configuration header summary,
3-22
,
7-16
PCI commands register,
3-23
,
7-16
status register,
3-24
,
7-16
retry
PCI transactions,
7-12
signals
DEVSEL,
2-35
,
7-7
error reporting signals,
9-5
FLSHREQ,
2-39
,
7-27
FRAME,
2-35
,
7-3
GNT,
2-35
,
7-3
IRDY,
2-36
,
7-3
ISA_MASTER,
2-39
,
7-26
LOCK,
2-36
,
7-23
MEMACK,
2-40
,
7-27
PERR,
2-37
,
7-26
,
9-5
REQ,
2-37
,
7-3
SERR,
2-38
,
7-26
,
9-5
TRDY,
2-38
,
7-3
target-abort error,
7-12
,
9-10
target-disconnect
,
7-2
,
7-12
,
8-4
target-initiated termination,
7-12
turnaround cycle,
7-8
PERR (PCI parity error) signal,
2-37
,
7-26
,
9-5
PICRs (processor interface configuration registers)
PICR1 register
address map A contiguity,
3-1
,
3-53
write
buffers
bit settings/overview,
3-52
,
4-5
CF_BREAD_WS bit,
3-52
,
4-5
,
4-19
FLASH_WR_EN bit,
3-54
,
9-6
LE_MODE (endian mode) bit,
3-55
,
3-68
,
B-5
MCP_EN bit,
4-20
,
9-3
speculative PCI reads bit,
3-55
ST_GATH_EN bit,
3-54
TEA_EN bit,
2-16
,
3-54
,
4-19
,
9-4
XIO_MODE bit,
3-1
,
3-53
PICR2 register
bit settings/overview,
3-58
,
4-5
CF_APARK bit,
3-55
,
4-5
CF_APHASE_WS bit,
3-62
,
4-5
CF_DOE bit,
3-62
,
5-26
CF_FAST_CASTOUT bit,
3-61
,
5-25
CF_HOLD bit,
3-61
,
5-24
CF_L2_HIT_DELAY bit,
3-61
,
4-21
,
5-25
CF_SNOOP_WS bit,
3-60
,
4-5
CF_TWO_BANKS bit,
3-61
,
5-7
CF_WDATA bit,
3-62
,
5-26
CF_WMODE bit,
3-60
,
5-27
FLASH_WR_LOCKOUT bit,
3-59
,
9-6
L2_EN bit,
3-58
,
3-69
,
5-23
TEA_EN bit,
3-69
Pipelined burst SRAMs
CF_WDATA bit,
3-62
,
5-26
description,
5-4
Pipelining
address pipelining,
4-7
,
4-10
memory
latency
,
4-7
split-bus transactions,
4-7
throughput
,
4-7
PLL
n
(clock mode) signals,
2-44
PMCR registers
refresh during power saving modes,
6-58
PMCR registers,
see
Power management
Power management
clock configuration,
A-6
doze mode,
6-28
,
A-3
DRAM refresh,
6-28
full-on mode,
6-28
,
A-3
memory interface, support,
6-28
,
6-58
memory refresh operation,
6-26
memory refresh operations,
A-7
modifying device drivers,
A-8
MPC106 default mode,
A-3
MPC106 support,
A-6
nap mode,
6-28
,
7-23
,
A-3
,
overview,
1-6
PCI address bus decoding,
A-7
PCI special-cycle operations,
7-22
PMCR registers
DRAM/EDO refresh configuration,
6-28
LP_REF_EN bit,
A-8