MOTOROLA
Chapter 7. PCI Bus Interface
7-11
Figure 7-4. PCI Burst Write Transaction
7.4.3 Transaction Termination
Termination of a PCI transaction may be initiated by either the master or the target. The
master is ultimately responsible for bringing all transactions to conclusion, regardless of the
cause of the termination. All transactions are concluded when FRAME and IRDY are both
negated, indicating the bus is idle.
7.4.3.1 Master-Initiated Termination
Normally, a master initiates termination by negating FRAME and asserting IRDY. This
indicates to the target that the final data phase is in progress. The final data transfer occurs
when both TRDY and IRDY are asserted. The transaction is considered complete when data
is transferred in the last data phase. After the final data phase, both FRAME and IRDY are
negated (the bus becomes idle).
There are three types of master-initiated termination:
Completion Completion refers to termination when the master has concluded its
intended transaction. This is the most common reason for termination.
Timeout
Timeout refers to termination when the master loses its bus grant
(GNT is negated) and its internal latency timer has expired. The
intended transaction is not necessarily concluded. Note that the
MPC106 does not have a latency timer. Latency for the MPC106
acting as a master is determined by the target.
Master-abort Master-abort is an abnormal case of master-initiated termination. If no
device (including the subtractive decoding agent) asserts DEVSEL to
claim a transaction, the master terminates the transaction with a
master-abort. For a master-abort termination, the master negates
FRAME and then negates IRDY on the next clock. If a transaction is
terminated by master-abort (except for a special-cycle command), the
received master-abort bit (bit 13) of the PCI status register is set.
SYSCLK
AD[31–0]
C/BE[3–0]
FRAME
IRDY
DEVSEL
TRDY
ADDR
CMD
DATA4
DATA3
DATA2
DATA1
BEs 4
BEs 3
BEs 2
BEs 1