
7-16
MPC106 PCIB/MC User's Manual
MOTOROLA
Table 7-2 summarizes the registers of the configuration header. Detailed descriptions of
these registers are provided in the
PCI Local Bus Specification
.
7.4.5.2 Accessing the PCI Configuration Space
To support hierarchical bridges, two types of configuration accesses are supported. The first
type of configuration access, type 0, is used to select a device on the local PCI bus (the PCI
bus connected to the MPC106). Type 0 configuration accesses are not propagated beyond
the local PCI bus and must be claimed by a local device or terminated with a master-abort.
The second type of configuration access, type 1, is used to pass a configuration request on
Table 7-2. PCI Configuration Space Header Summary
Address
Offset
Register Name
Description
00
Vendor ID
Identifies the manufacturer of the device (assigned by the PCI SIG
(special-interest group) to ensure uniqueness)
02
Device ID
Identifies the particular device (assigned by the vendor)
04
Command
Provides coarse control over a device’s ability to generate and respond
to PCI bus cycles
06
Status
Records status information for PCI bus-related events
08
Revision ID
Specifies a device-specific revision code (assigned by vendor)
09
Class code
Identifies the generic function of the device and (in some cases) a
specific register-level programming interface
0C
Cache line size
Specifies the system cache line size in 32-bit units
0D
Latency timer
Specifies the value of the latency timer for this bus master in PCI bus
clock units
0E
Header type
Bits 0–6 identify the layout of bytes 10–3F; bit 7 indicates a multifunction
device. The most common header type (0x00) is shown in Figure 7-6
and in this table.
0F
BIST
Optional register for control and status of built-in self test (BIST)
10–27
Base address registers
Address mapping information for memory and I/O space
28
—
Reserved for future use
2C
—
Reserved for future use
30
Expansion ROM base
address
Base address and size information for expansion ROM contained in an
add-on board
34
—
Reserved for future use
38
—
Reserved for future use
3C
Interrupt line
Contains interrupt line routing information
3D
Interrupt pin
Indicates which interrupt pin the device (or function) uses
3E
Min_Gnt
Specifies the length of the device’s burst period in 0.25
μ
s units
3F
Max_Lat
Specifies how often the device needs to gain access to the bus in 0.25
μ
s units